Inverters designed using reduced active semiconductor devices can be of interest to the industry because of their lower cost and enhanced reliability linked to their less complex gating and control circuitries. Despite their simplicity, most of the reduced component count inverters reported to date can only either perform voltage-buck or boost operation with buck-boost operation usually attained by adding additional actively controlled dc-dc converters. Although effective, the adding of dc-dc converters introduces additional active switches, which somehow dilute advantages associated with a reduced component count topology. Proposing alternative configurations with a reduced active semiconductor count, this paper discusses the systematic design of a number of Z-source B4 inverters, whose buck-boost capability is attained passively by inserting LC elements and clamping diodes. Visually, the proposed inverters are configured to actively supply two phases of a three-phase load with the third phase passively clamped using clamping diodes. The inverters can operate without dead-time protection, which together with the lower active element count, further simplify the inverter control and gating circuitries, hence enhancing reliability. To validate the inverter performance and practicality, experimental testing is performed with a set of representative results presented in the paper for viewing. Advantages and disadvantages of the proposed inverters, as compared to existing circuitries, are also discussed in the paper.
|Titel||IEEE Power Electronics Specialists Conference, PESC 2007|
|Forlag||Electrical Engineering/Electronics, Computer, Communications and Information Technology Association|
|Status||Udgivet - 2007|
|Begivenhed||Power Electronics Specialists Conference, PESC 2007 - Orlando, Florida, USA|
Varighed: 17 jun. 2007 → 21 jun. 2007
|Konference||Power Electronics Specialists Conference, PESC 2007|
|Periode||17/06/2007 → 21/06/2007|