Project Details
Description
EMBSYS Performance evaluation of cache memory architectures in modern superscalar and VLIW DSP processors. The project looks into various HLL constructs and their compilation onto state-of-the-art DSP processors, primarily from a cache perspective. Egidijus Kazanavicius, Ole Olsen
Status | Finished |
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Effective start/end date | 31/12/2001 → 31/12/2001 |