Abstract
Stub Series Terminated Logic (SSTL) is an Input/output standard. It is used to match the impedance of line, port and device of our design under consideration. Therefore, selection of energy efficient SSTL I/O standard among available different class of SSTL logic family in FPGA, plays a vital role to achieve energy efficiency in design under test (DUT). Here, DUT is ROM. ROM is an integral part of processor. Therefore, energy efficient design of RAM is a building block of energy efficient processor. We are using Verilog hardware description language, Virtex-6 FPGA, and Xilinx ISE simulator. We are operating ROM with the highest operating frequency of 4th generation i7 processor to test the compatibility of this design with the latest hardware in use. When there is no demand of peak performance, then we can save 74.5% clock power, 75% signal power, and 30.83% I/O power by operating our device with 1GHz frequency in place of 4GHz. There is no change in clock power and signal power but SSTL2_II_DCI having 80.24%, 83.38%, 62.92%, and 76.52% and 83.03% more I/O power consumption with respect to SSTL2_I, SST18_I, SSTL2_I_DCI, SSTL2_II, and SSTL15 respectively at 3.3GHz.
Original language | English |
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Title of host publication | Proceedings of the 3rd International Symposium on Environment-Friendly Energies and Applications (EFEA 2014) |
Number of pages | 6 |
Place of Publication | Paris, France |
Publisher | IEEE Press |
Publication date | Nov 2014 |
DOIs | |
Publication status | Published - Nov 2014 |
Event | 3rd International Symposium on Environment-Friendly Energies and Applications (EFEA 2014) - Paris, France Duration: 19 Nov 2014 → 21 Nov 2014 |
Conference
Conference | 3rd International Symposium on Environment-Friendly Energies and Applications (EFEA 2014) |
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Country/Territory | France |
City | Paris |
Period | 19/11/2014 → 21/11/2014 |
Keywords
- I/O standard
- Thermal Analysis
- SSTL
- Power Optimized Design
- I/Os Power