TY - GEN
T1 - 6kV/400A Switching Demonstration of a 10kV SiC MOSFET Half-bridge Module in an Industry Standard Package
AU - Qi, Nianzun
AU - Yan, Zhixing
AU - Liu, Gao
AU - Meyer, Stefan
AU - Beczkowski, Szymon Michal
AU - Jørgensen, Asger Bjørn
AU - Takahashi, Masaki
AU - Nielsen, Morten Rahr
AU - Jørgensen, Jannick Kjær
AU - Sun, Zhongchao
AU - Zhao, Hongbo
AU - Rannestad, Bjørn
AU - Bech, Michael Møller
AU - Munk-Nielsen, Stig
PY - 2025/11/10
Y1 - 2025/11/10
N2 - The 10 kV SiC MOSFET is a promising technology for revolutionizing medium- and high-voltage systems owing to its high blocking voltage and fast switching capability. However, existing power module design practices, largely inherited from Si IGBT and low-voltage SiC devices, must be tailored to address the unique challenges of 10 kV SiC MOSFETs, such as strong sensitivity to parasitic capacitances and severe inter-chip oscillations. This paper proposes a novel module package that incorporates two innovative techniques: (1) a lifted output busbar, designed to mitigate the parasitic capacitive coupling, and (2) a partitioned device layout scheme, which suppress inter-chip oscillations. These approaches not only mitigate the aforementioned challenges but also maintain compatibility with industry-standard package dimensions. The effectiveness of the proposed design is validated through both static and dynamic testing. Experimental results demonstrate the successful realization of the first 10 kV power module with high power density and robust switching performance at 6000 V/400 A, marking a step toward practical deployment of multichip 10 kV SiC MOSFET modules in high-power applications.
AB - The 10 kV SiC MOSFET is a promising technology for revolutionizing medium- and high-voltage systems owing to its high blocking voltage and fast switching capability. However, existing power module design practices, largely inherited from Si IGBT and low-voltage SiC devices, must be tailored to address the unique challenges of 10 kV SiC MOSFETs, such as strong sensitivity to parasitic capacitances and severe inter-chip oscillations. This paper proposes a novel module package that incorporates two innovative techniques: (1) a lifted output busbar, designed to mitigate the parasitic capacitive coupling, and (2) a partitioned device layout scheme, which suppress inter-chip oscillations. These approaches not only mitigate the aforementioned challenges but also maintain compatibility with industry-standard package dimensions. The effectiveness of the proposed design is validated through both static and dynamic testing. Experimental results demonstrate the successful realization of the first 10 kV power module with high power density and robust switching performance at 6000 V/400 A, marking a step toward practical deployment of multichip 10 kV SiC MOSFET modules in high-power applications.
U2 - 10.1109/WiPDA63755.2025.11303419
DO - 10.1109/WiPDA63755.2025.11303419
M3 - Article in proceeding
BT - 2025 IEEE 12th Workshop on Wide Bandgap Power Devices and Applications (WiPDA)
PB - IEEE Xplore
T2 - 2025 IEEE 12th Workshop on Wide Bandgap Power Devices and Applications (WiPDA)
Y2 - 10 November 2025 through 12 November 2025
ER -