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Abstract
This article proposes a capacitor voltage ripple reduction method used for a modular multilevel cascade converter (MMCC) with single delta bridge cells (SDBC), by applying a third harmonic zero-sequence current. A practical case study on an 80 MVar/33 kV MMCC-SDBC-based STATCOM is used to demonstrate the method. The impact of the third harmonic zero-sequence current level of the capacitor ripple reduction and the electrothermal stresses on insulated gate bipolar transistor modules are analyzed. An optimal parameter of the current level is obtained by compromising the above-mentioned performance factors. The obtained result shows that the required capacitance, as well as the capacitor bank volume, is reduced by 20% without increasing the total power semiconductor losses by using the proposed method.
Original language | English |
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Article number | 8792104 |
Journal | IEEE Transactions on Industry Applications |
Volume | 55 |
Issue number | 6 |
Pages (from-to) | 6115 - 6126 |
Number of pages | 12 |
ISSN | 0093-9994 |
DOIs | |
Publication status | Published - Nov 2019 |
Keywords
- Modular Multilevel cascade Converter
- STATCOM
- Capacitor voltage ripple reduction
- Zero-sequence current
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Dive into the research topics of 'A DC-Link Capacitor Voltage Ripple Reduction Method for a Modular Multilevel Cascade Converter With Single Delta Bridge Cells'. Together they form a unique fingerprint.Projects
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Reliability evaluation methodology for power electronics system
Blaabjerg, F., Wang, H., Bahrebar, S. & Gui, Y.
01/10/2017 → 30/09/2019
Project: Research