A Method for A Priori Implementation Effort Estimation for Hardware Design

Rasmus Abildgren; Jean-Philippe Diguet; Guy Gogniat; Pierre Bomel; Peter Koch; Yannick Le Moullec

doi:10.1109/ICED.2008.4786735

A Method for A Priori Implementation Effort Estimation for Hardware Design

Rasmus Abildgren, Jean-Philippe Diguet, Guy Gogniat, Pierre Bomel, Peter Koch, Yannick Le Moullec

Research output: Contribution to book/anthology/report/conference proceeding › Article in proceeding › Research › peer-review

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Abstract

This paper presents a metric-based approach for estimating the hardware implementation effort (in terms of time) for an application in relation to the number of independent paths of its algorithms. We define a metric which exploits the relation between the number of independent paths in an algorithm and the corresponding implementation effort. Furthermore, we complement the metric with a correction function taking the designer's experience into account. Our experimental results show that with the proposed approach it is possible to estimate the hardware implementation effort, and thereby facilitating designers and managers needs for estimating the time-to-market schedule.

Original language	English
Title of host publication	International Conference on Electronic Design, 2008. ICED 2008
Number of pages	6
Publisher	IEEE
Publication date	2008
ISBN (Electronic)	978-1-4244-2315-6
DOIs	https://doi.org/10.1109/ICED.2008.4786735
Publication status	Published - 2008
Event	International Conference on Electronic Design (ICED) 2008 - Penang, Malaysia Duration: 1 Dec 2008 → 3 Dec 2008 Conference number: 1

Conference

Conference	International Conference on Electronic Design (ICED) 2008
Number	1
Country/Territory	Malaysia
City	Penang
Period	01/12/2008 → 03/12/2008

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Methods for accelerated design for FPGA technology
Abildgren, R., Koch, P., Le Moullec, Y. & Knudsen, R. B.
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01/10/2005 → 01/05/2009
Project: Research

Cite this

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title = "A Method for A Priori Implementation Effort Estimation for Hardware Design",

abstract = "This paper presents a metric-based approach for estimating the hardware implementation effort (in terms of time) for an application in relation to the number of independent paths of its algorithms. We define a metric which exploits the relation between the number of independent paths in an algorithm and the corresponding implementation effort. Furthermore, we complement the metric with a correction function taking the designer's experience into account. Our experimental results show that with the proposed approach it is possible to estimate the hardware implementation effort, and thereby facilitating designers and managers needs for estimating the time-to-market schedule. ",

author = "Rasmus Abildgren and Jean-Philippe Diguet and Guy Gogniat and Pierre Bomel and Peter Koch and {Le Moullec}, Yannick",

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AU - Diguet, Jean-Philippe

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AU - Koch, Peter

AU - Le Moullec, Yannick

N1 - Conference code: 1

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N2 - This paper presents a metric-based approach for estimating the hardware implementation effort (in terms of time) for an application in relation to the number of independent paths of its algorithms. We define a metric which exploits the relation between the number of independent paths in an algorithm and the corresponding implementation effort. Furthermore, we complement the metric with a correction function taking the designer's experience into account. Our experimental results show that with the proposed approach it is possible to estimate the hardware implementation effort, and thereby facilitating designers and managers needs for estimating the time-to-market schedule.

AB - This paper presents a metric-based approach for estimating the hardware implementation effort (in terms of time) for an application in relation to the number of independent paths of its algorithms. We define a metric which exploits the relation between the number of independent paths in an algorithm and the corresponding implementation effort. Furthermore, we complement the metric with a correction function taking the designer's experience into account. Our experimental results show that with the proposed approach it is possible to estimate the hardware implementation effort, and thereby facilitating designers and managers needs for estimating the time-to-market schedule.

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DO - 10.1109/ICED.2008.4786735

M3 - Article in proceeding

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PB - IEEE

T2 - International Conference on Electronic Design (ICED) 2008

Y2 - 1 December 2008 through 3 December 2008

ER -

A Method for A Priori Implementation Effort Estimation for Hardware Design

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Methods for accelerated design for FPGA technology

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