TY - JOUR
T1 - A Novel Submodule Voltage Balancing Scheme for Modular Multilevel Cascade Converter—Double-Star Chopper-Cells (MMCC-DSCC) Based STATCOM
AU - Jin, Y.
AU - Xiao, Qian
AU - Dong, Chaoyu
AU - Jia, Hongjie
AU - Mu, Yunfei
AU - Xie, Bing
AU - Ji, Yanchao
AU - Chaudhary, Sanjay Kumar
AU - Teodorescu, Remus
PY - 2019/6
Y1 - 2019/6
N2 - A novel capacitor voltage balancing scheme for modular multilevel cascade converter-double-star chopper-cells (MMCC-DSCC)-based STATCOM is proposed in this paper. Compared with the conventional software voltage balancing methods, the proposed scheme has three main advantages. First, only six voltage sensors are needed, and other voltage sensors have been removed. Then, the control framework can be simple without sort and select process, or some balancing control loops. Additional delay process caused by the sampling and control signals transmission is also mitigated. Finally, the faster capacitor balancing speed can be obtained. In addition, compared with some other hardware voltage balancing schemes, there are superior characteristics in terms of the reduced number of switches and only the popular power modules in the additional units are applied. For these additional modules, the parameters design guide of the proposed scheme has been discussed. Verified results from the 13-level simulated system and 9-level experimental platform for the MMCC-DSCC based STATCOM show the effectiveness of the proposed scheme. By the proposed scheme, both DC capacitor voltage balancing control and reactive power compensation are simultaneously realized for the MMCC-DSCC-based STATCOM even in balanced and unbalanced load.
AB - A novel capacitor voltage balancing scheme for modular multilevel cascade converter-double-star chopper-cells (MMCC-DSCC)-based STATCOM is proposed in this paper. Compared with the conventional software voltage balancing methods, the proposed scheme has three main advantages. First, only six voltage sensors are needed, and other voltage sensors have been removed. Then, the control framework can be simple without sort and select process, or some balancing control loops. Additional delay process caused by the sampling and control signals transmission is also mitigated. Finally, the faster capacitor balancing speed can be obtained. In addition, compared with some other hardware voltage balancing schemes, there are superior characteristics in terms of the reduced number of switches and only the popular power modules in the additional units are applied. For these additional modules, the parameters design guide of the proposed scheme has been discussed. Verified results from the 13-level simulated system and 9-level experimental platform for the MMCC-DSCC based STATCOM show the effectiveness of the proposed scheme. By the proposed scheme, both DC capacitor voltage balancing control and reactive power compensation are simultaneously realized for the MMCC-DSCC-based STATCOM even in balanced and unbalanced load.
KW - choppers (circuits)
KW - electric current control
KW - machine control
KW - power capacitors
KW - power convertors
KW - static VAr compensators
KW - voltage control
KW - balancing control loops
KW - control signals transmission
KW - hardware voltage balancing schemes
KW - DC capacitor voltage balancing control
KW - MMCC-DSCC-based STATCOM
KW - balanced load
KW - unbalanced load
KW - modular multilevel cascade converter-double-star chopper-cells-based STATCOM
KW - voltage sensors
KW - control framework
KW - delay process
KW - capacitor voltage
KW - submodule voltage balancing scheme
KW - capacitor balancing speed
KW - Topology
KW - Capacitors
KW - Sensors
KW - Automatic voltage control
KW - Sorting
KW - Switches
KW - Diode-clamped circuit
KW - double-star chopper-cell (DSCC)
KW - modular multilevel cascade converter (MMCC)
KW - voltage balancing
KW - STATCOM
KW - Diode-clamped circuit
KW - Double-star chopper-cell (DSCC)
KW - Modular multilevel cascade converter (MMCC)
KW - Voltage balancing
KW - STATCOM
UR - http://www.scopus.com/inward/record.url?scp=85068682214&partnerID=8YFLogxK
U2 - 10.1109/ACCESS.2019.2924609
DO - 10.1109/ACCESS.2019.2924609
M3 - Journal article
SN - 2169-3536
VL - 7
SP - 83058
EP - 83073
JO - IEEE Access
JF - IEEE Access
M1 - 8744284
ER -