An active two-terminal capacitor device with a controllable capacitance based on a capacitance value input C_I. A processor system PRS executes an algorithm which controls a power converter PCV with controllable electric switches connected to the two external terminals A, B along with a fixed value capacitor component CI. Based on sampling of at least the voltage across the capacitor component CI, the algorithm controls the power converter PCV to provide a resulting capacitance across the external terminals A, B which serves to match the capacitance value in ut C_I.
|IPC||H02M 1/15 (2006.01), H02J 1/02 (2006.01), H02J 1/14 (2006.01), H03K 17/687|
|Publication status||Published - Aug 2019|
Bibliographical notePub. No.: WO/2019/161866
International Application No.: PCT/DK2019/050063