Abstract
The virtual output impedance loop is known as an effective way to enhance the load sharing stability and quality of droop-controlled parallel inverters. This paper proposes an improved design of virtual output impedance loop for parallel three-phase voltage source inverters. In the approach, a virtual output impedance loop based on the decomposition of inverter output current is developed, where the positive- and negative-sequence virtual impedances are synthesized separately. Thus, the negative-sequence circulating current among the parallel inverters can be minimized by using a large negative-sequence virtual resistance even in the case of feeding a balanced three-phase load. Furthermore, to adapt to the variety of unbalanced loads, a dynamically-tuned negative-sequence resistance loop is designed, such that a good compromise between the quality of inverter output voltage and the performance of load sharing can be obtained. Finally, laboratory test results of two parallel three-phase voltage source inverters are shown to confirm the validity of the proposed method.
Original language | English |
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Title of host publication | Proceedings of the IEEE Energy Conversion Congress and Exposition 2012 |
Place of Publication | Raleigh, NC |
Publisher | IEEE Press |
Publication date | 2012 |
Pages | 2466-2473 |
ISBN (Print) | 978-1-4673-0802-1 |
ISBN (Electronic) | 978-1-4673-0801-4 |
DOIs | |
Publication status | Published - 2012 |
Event | the Fourth IEEE Energy Conversion Congress and Exposition, ECCE 2012 - Raleigh Convention Center, Raleigh, United States Duration: 15 Sept 2012 → 20 Sept 2012 |
Conference
Conference | the Fourth IEEE Energy Conversion Congress and Exposition, ECCE 2012 |
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Location | Raleigh Convention Center |
Country/Territory | United States |
City | Raleigh |
Period | 15/09/2012 → 20/09/2012 |