Analysis and Mitigation Methods of Gate Oscillation in Paralleled 10 kV SiC MOSFETs

Keyphrases

• Gate Oscillations 100%
• 10 kV SiC MOSFET 100%
• Mitigation Methods 100%
• SiC MOSFET 50%
• MOSFET 33%
• Closed-loop Feedback System 33%
• Switching Devices 16%
• Switching Behavior 16%
• Parasitic Capacitance 16%
• Switching Transients 16%
• Circuit Model 16%
• Power Module 16%
• Small-signal Model 16%
• Saturation Region 16%
• Parasitic Parameters 16%
• Inter-module Connection 16%
• Parasitic Inductance 16%
• Oscillation Mechanism 16%
• Paralleled SiC MOSFETs 16%
• Transconductance 16%
• Double Pulse Test 16%
• External Connection 16%
• Device Damage 16%

Engineering

• Metal-Oxide-Semiconductor Field-Effect Transistor 100%
• Mosfets 100%
• Closed Loop 50%
• Circuit Model 50%
• Good Prediction 25%
• Pulse Test 25%
• Power Mosfets 25%
• Saturation Region 25%
• Signal Circuit 25%

Computer Science

• Saturation Region 100%