Analysis of phase-locked loop influence on the stability of single-phase grid-connected inverter

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Abstract

A controlled power inverter can cause instability at the point of common coupling (PCC) with its output filter and the grid. This paper analyzes the influence of the Phase-Locked Loop (PLL) on the output admittance of single-phase current-controlled inverters with different grid stiffness. It shows that the PLL introduces a paralleled admittance into the output admittance of the inverter, which may lead to unintentional low-order harmonic oscillation in a weak grid. Moreover, the Second Order Generalized Integrator PLL (SOGI-PLL) is also modeled. It is found that the quadrature signal generator of SOGI plays a stabilizing role in grid-inverter interactions, which thus provides a promising candidate for avoiding the PLL-induced instability in single-phase inverters. Simulation results are presented for verifying the theoretical analysis. The possible instability due to different PLL bandwidth is also demonstrated.
Original languageEnglish
Title of host publicationProceedings of the 2015 IEEE 6th International Symposium on Power Electronics for Distributed Generation Systems (PEDG)
PublisherIEEE Press
Publication dateJun 2015
Pages1-8
DOIs
Publication statusPublished - Jun 2015
EventIEEE 6th International Symposium on Power Electronics for Distributed Generation Systems, PEDG 2015 - Pullman Aachen Quellenhof hotel, Aachen, Germany
Duration: 22 Sep 201525 Sep 2015

Conference

ConferenceIEEE 6th International Symposium on Power Electronics for Distributed Generation Systems, PEDG 2015
LocationPullman Aachen Quellenhof hotel
CountryGermany
CityAachen
Period22/09/201525/09/2015

Keywords

  • Phase-Locked Loop (PLL)
  • Small-signal model
  • Single-phase inverter
  • Stability

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