Architectural Design Space Exploration of an FPGA-based Compressed Sampling Engine: Application to Wireless Heart-Rate Monitoring

Mohammad El-Sayed; Peter Koch; Yannick Le Moullec

doi:10.1109/NORCHIP.2015.7364369

Architectural Design Space Exploration of an FPGA-based Compressed Sampling Engine: Application to Wireless Heart-Rate Monitoring

Mohammad El-Sayed, Peter Koch, Yannick Le Moullec

Department of Electronic Systems

Research output: Contribution to book/anthology/report/conference proceeding › Article in proceeding › Research › peer-review

1 Citation (Scopus)

Abstract

We present the architectural design space exploration of a compressed sampling engine for use in a wireless heart-rate monitoring system. We show how parallelism affects execution time at the register transfer level. Furthermore, two example solutions (modified semi-parallel and full-parallel) selected from the design space are prototyped on an Altera Cyclone III FPGA platform; in both cases the FPGA resource usage is less than 1% and the maximum frequency is 250 MHz.

Original language	English
Title of host publication	Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015
Number of pages	5
Publisher	IEEE Press
Publication date	2015
Pages	1-5
ISBN (Electronic)	978-1-4673-6576-5
DOIs	https://doi.org/10.1109/NORCHIP.2015.7364369
Publication status	Published - 2015
Event	Nordic Circuits and Systems Conference (NORCAS) - Oslo, Norway Duration: 26 Oct 2015 → 28 Oct 2015

Conference

Conference	Nordic Circuits and Systems Conference (NORCAS)
Location	Oslo
Country/Territory	Norway
Period	26/10/2015 → 28/10/2015

Access to Document

10.1109/NORCHIP.2015.7364369

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Cite this

@inproceedings{7d13643997194a8fae2def1e2094cb01,

title = "Architectural Design Space Exploration of an FPGA-based Compressed Sampling Engine: Application to Wireless Heart-Rate Monitoring",

abstract = "We present the architectural design space exploration of a compressed sampling engine for use in a wireless heart-rate monitoring system. We show how parallelism affects execution time at the register transfer level. Furthermore, two example solutions (modified semi-parallel and full-parallel) selected from the design space are prototyped on an Altera Cyclone III FPGA platform; in both cases the FPGA resource usage is less than 1% and the maximum frequency is 250 MHz.",

author = "Mohammad El-Sayed and Peter Koch and {Le Moullec}, Yannick",

year = "2015",

doi = "10.1109/NORCHIP.2015.7364369",

language = "English",

pages = "1--5",

booktitle = "Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015",

publisher = "IEEE Press",

note = "Nordic Circuits and Systems Conference (NORCAS) ; Conference date: 26-10-2015 Through 28-10-2015",

}

El-Sayed, M, Koch, P & Le Moullec, Y 2015, Architectural Design Space Exploration of an FPGA-based Compressed Sampling Engine: Application to Wireless Heart-Rate Monitoring. in Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015. IEEE Press, pp. 1-5, Nordic Circuits and Systems Conference (NORCAS), Norway, 26/10/2015. https://doi.org/10.1109/NORCHIP.2015.7364369

Architectural Design Space Exploration of an FPGA-based Compressed Sampling Engine: Application to Wireless Heart-Rate Monitoring. / El-Sayed, Mohammad; Koch, Peter; Le Moullec, Yannick.
Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015. IEEE Press, 2015. p. 1-5.

Research output: Contribution to book/anthology/report/conference proceeding › Article in proceeding › Research › peer-review

TY - GEN

T1 - Architectural Design Space Exploration of an FPGA-based Compressed Sampling Engine

T2 - Nordic Circuits and Systems Conference (NORCAS)

AU - El-Sayed, Mohammad

AU - Koch, Peter

AU - Le Moullec, Yannick

PY - 2015

Y1 - 2015

N2 - We present the architectural design space exploration of a compressed sampling engine for use in a wireless heart-rate monitoring system. We show how parallelism affects execution time at the register transfer level. Furthermore, two example solutions (modified semi-parallel and full-parallel) selected from the design space are prototyped on an Altera Cyclone III FPGA platform; in both cases the FPGA resource usage is less than 1% and the maximum frequency is 250 MHz.

AB - We present the architectural design space exploration of a compressed sampling engine for use in a wireless heart-rate monitoring system. We show how parallelism affects execution time at the register transfer level. Furthermore, two example solutions (modified semi-parallel and full-parallel) selected from the design space are prototyped on an Altera Cyclone III FPGA platform; in both cases the FPGA resource usage is less than 1% and the maximum frequency is 250 MHz.

U2 - 10.1109/NORCHIP.2015.7364369

DO - 10.1109/NORCHIP.2015.7364369

M3 - Article in proceeding

SP - 1

EP - 5

BT - Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015

PB - IEEE Press

Y2 - 26 October 2015 through 28 October 2015

ER -