Automated gate impedance network design for SiC MOSFETs using SPICE solver interfaced with MATLAB environment

Pawel Piotr Kubulus; Szymon Michal Beczkowski; Stig Munk-Nielsen; Asger Bjørn Jørgensen

Automated gate impedance network design for SiC MOSFETs using SPICE solver interfaced with MATLAB environment

Pawel Piotr Kubulus^*, Szymon Michal Beczkowski, Stig Munk-Nielsen, Asger Bjørn Jørgensen

^*Corresponding author for this work

Research output: Contribution to book/anthology/report/conference proceeding › Article in proceeding › Research › peer-review

91 Downloads (Pure)

Abstract

In order to ensure proper switching of SiC devices gate impedance has to be carefully selected. Chosen topology and parameter values allow for damping the oscillations in poorly designed layouts, as well as adjusting dV/dt levels in cases where layout allows for too fast switching. Due to a wide choice of gate impedance topologies, some with multiple tunable parameters, experimental fine-tuning is a time-consuming process and analytical predictions do not take full effect of the parasitic elements into account. For this reason, an automated design process is developed using Matlab and LTSpice and the results are verified experimentally in a Double Pulse Test(DPT) setup, for the prediction accuracy assessment.

Original language	English
Title of host publication	2022 24th European Conference on Power Electronics and Applications (EPE'22 ECCE Europe)
Number of pages	9
Publisher	IEEE (Institute of Electrical and Electronics Engineers)
Publication date	Oct 2022
ISBN (Electronic)	9789075815399
Publication status	Published - Oct 2022
Event	2022 24th European Conference on Power Electronics and Applications (EPE'22 ECCE Europe) - Hanover, Germany, Hanover, Germany Duration: 5 Sept 2022 → 9 Sept 2022

Conference

Conference	2022 24th European Conference on Power Electronics and Applications (EPE'22 ECCE Europe)
Location	Hanover, Germany
Country/Territory	Germany
City	Hanover
Period	05/09/2022 → 09/09/2022

Keywords

Design optimization
MOSFET
Parasitic elements Silicon Carbide (SiC> Virtual prototyping >>

Access to Document

0379-epe2022-full-15341524Accepted author manuscript, 2.72 MB

https://ieeexplore.ieee.org/document/9907388

AUB Link

Search for the material in Aalborg University Library's search engine

Cite this

Kubulus, P. P., Beczkowski, S. M., Munk-Nielsen, S., & Jørgensen, A. B. (2022). Automated gate impedance network design for SiC MOSFETs using SPICE solver interfaced with MATLAB environment. In 2022 24th European Conference on Power Electronics and Applications (EPE'22 ECCE Europe) IEEE (Institute of Electrical and Electronics Engineers). https://ieeexplore.ieee.org/document/9907388

@inproceedings{f82df5d8449a4880bf04c9035ae17b08,

title = "Automated gate impedance network design for SiC MOSFETs using SPICE solver interfaced with MATLAB environment",

abstract = "In order to ensure proper switching of SiC devices gate impedance has to be carefully selected. Chosen topology and parameter values allow for damping the oscillations in poorly designed layouts, as well as adjusting dV/dt levels in cases where layout allows for too fast switching. Due to a wide choice of gate impedance topologies, some with multiple tunable parameters, experimental fine-tuning is a time-consuming process and analytical predictions do not take full effect of the parasitic elements into account. For this reason, an automated design process is developed using Matlab and LTSpice and the results are verified experimentally in a Double Pulse Test(DPT) setup, for the prediction accuracy assessment.",

keywords = "Design optimization, MOSFET, Parasitic elements Silicon Carbide (SiC> Virtual prototyping >>",

author = "Kubulus, {Pawel Piotr} and Beczkowski, {Szymon Michal} and Stig Munk-Nielsen and J{\o}rgensen, {Asger Bj{\o}rn}",

year = "2022",

month = oct,

language = "English",

booktitle = "2022 24th European Conference on Power Electronics and Applications (EPE'22 ECCE Europe)",

publisher = "IEEE (Institute of Electrical and Electronics Engineers)",

address = "United States",

note = "2022 24th European Conference on Power Electronics and Applications (EPE'22 ECCE Europe) ; Conference date: 05-09-2022 Through 09-09-2022",

}

Kubulus, PP , Beczkowski, SM , Munk-Nielsen, S & Jørgensen, AB 2022, Automated gate impedance network design for SiC MOSFETs using SPICE solver interfaced with MATLAB environment. in 2022 24th European Conference on Power Electronics and Applications (EPE'22 ECCE Europe). IEEE (Institute of Electrical and Electronics Engineers), 2022 24th European Conference on Power Electronics and Applications (EPE'22 ECCE Europe), Hanover, Germany, 05/09/2022. <https://ieeexplore.ieee.org/document/9907388>

Automated gate impedance network design for SiC MOSFETs using SPICE solver interfaced with MATLAB environment. / Kubulus, Pawel Piotr ; Beczkowski, Szymon Michal ; Munk-Nielsen, Stig et al.
2022 24th European Conference on Power Electronics and Applications (EPE'22 ECCE Europe). IEEE (Institute of Electrical and Electronics Engineers), 2022.

Research output: Contribution to book/anthology/report/conference proceeding › Article in proceeding › Research › peer-review

TY - GEN

T1 - Automated gate impedance network design for SiC MOSFETs using SPICE solver interfaced with MATLAB environment

AU - Kubulus, Pawel Piotr

AU - Beczkowski, Szymon Michal

AU - Munk-Nielsen, Stig

AU - Jørgensen, Asger Bjørn

PY - 2022/10

Y1 - 2022/10

N2 - In order to ensure proper switching of SiC devices gate impedance has to be carefully selected. Chosen topology and parameter values allow for damping the oscillations in poorly designed layouts, as well as adjusting dV/dt levels in cases where layout allows for too fast switching. Due to a wide choice of gate impedance topologies, some with multiple tunable parameters, experimental fine-tuning is a time-consuming process and analytical predictions do not take full effect of the parasitic elements into account. For this reason, an automated design process is developed using Matlab and LTSpice and the results are verified experimentally in a Double Pulse Test(DPT) setup, for the prediction accuracy assessment.

AB - In order to ensure proper switching of SiC devices gate impedance has to be carefully selected. Chosen topology and parameter values allow for damping the oscillations in poorly designed layouts, as well as adjusting dV/dt levels in cases where layout allows for too fast switching. Due to a wide choice of gate impedance topologies, some with multiple tunable parameters, experimental fine-tuning is a time-consuming process and analytical predictions do not take full effect of the parasitic elements into account. For this reason, an automated design process is developed using Matlab and LTSpice and the results are verified experimentally in a Double Pulse Test(DPT) setup, for the prediction accuracy assessment.

KW - Design optimization

KW - MOSFET

KW - Parasitic elements Silicon Carbide (SiC> Virtual prototyping >>

UR - http://www.scopus.com/inward/record.url?scp=85141588717&partnerID=8YFLogxK

M3 - Article in proceeding

BT - 2022 24th European Conference on Power Electronics and Applications (EPE'22 ECCE Europe)

PB - IEEE (Institute of Electrical and Electronics Engineers)

T2 - 2022 24th European Conference on Power Electronics and Applications (EPE'22 ECCE Europe)

Y2 - 5 September 2022 through 9 September 2022

ER -

Automated gate impedance network design for SiC MOSFETs using SPICE solver interfaced with MATLAB environment

Abstract

Conference

Keywords

Access to Document

AUB Link

Other files and links

Fingerprint

CoDE: Center of Digitalized Electronics (CoDE)

Digital Twin Based Automated Design for Converters Incorporating Wide-Band Gap Devices

Cite this

Automated gate impedance network design for SiC MOSFETs using SPICE solver interfaced with MATLAB environment

Abstract

Conference

Keywords

Access to Document

AUB Link

Other files and links

Fingerprint

Projects

CoDE: Center of Digitalized Electronics (CoDE)

Digital Twin Based Automated Design for Converters Incorporating Wide-Band Gap Devices

Cite this