Projects per year
In order to ensure proper switching of SiC devices gate impedance has to be carefully selected. Chosen topology and parameter values allow for damping the oscillations in poorly designed layouts, as well as adjusting dV/dt levels in cases where layout allows for too fast switching. Due to a wide choice of gate impedance topologies, some with multiple tunable parameters, experimental fine-tuning is a time-consuming process and analytical predictions do not take full effect of the parasitic elements into account. For this reason, an automated design process is developed using Matlab and LTSpice and the results are verified experimentally in a Double Pulse Test(DPT) setup, for the prediction accuracy assessment.
|Title of host publication||2022 24th European Conference on Power Electronics and Applications (EPE'22 ECCE Europe)|
|Number of pages||9|
|Publication date||Oct 2022|
|Publication status||Published - Oct 2022|
|Event||2022 24th European Conference on Power Electronics and Applications (EPE'22 ECCE Europe) - Hanover, Germany, Hanover, Germany|
Duration: 5 Sep 2022 → 9 Sep 2022
|Conference||2022 24th European Conference on Power Electronics and Applications (EPE'22 ECCE Europe)|
|Period||05/09/2022 → 09/09/2022|
- Design optimization
- Parasitic elements Silicon Carbide (SiC> Virtual prototyping >>
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- 2 Active
Digital Twin Based Automated Design for Converters Incorporating Wide-Band Gap Devices
Kubulus, P. P., Munk-Nielsen, S. & Jørgensen, A. B.
01/09/2021 → 31/08/2024
Project: PhD Project
CoDE: Center of Digitalized Electronics (CoDE)
Munk-Nielsen, S., Jørgensen, A. B., Uhrenfeldt, C., Beczkowski, S. M., Ahmad, F., Meinert, J. D., Kubulus, P. P., Takahashi, M., Sun, Z., Wang, R., Gao, Y., Zäch, M. R. & Steffensen, B.
01/01/2021 → 31/12/2025