TY - JOUR
T1 - Control strategies of mitigating dead-time effect on power converters
T2 - An overview
AU - Ji, Yi
AU - Yang, Yong
AU - Zhou, Jiale
AU - Ding, Hao
AU - Guo, Xiaoqiang
AU - Padmanaban, Sanjeevikumar
PY - 2019/2
Y1 - 2019/2
N2 - To prevent short-circuits between the upper and lower switches of power converters from over-current protection, the dead time is mandatory in the switching gating signal for voltage source converters. However, this results in many negative effects on system operations, such as output voltage and current distortions (e.g., increased level of fifth and seventh harmonics), zero-current-clamping phenomenon, and output fundamental-frequency voltage reduction. Many solutions have been presented to cope with this problem. First, the dead-time effect is analyzed by taking into account factors such as the zero-clamping phenomenon, voltage drops on diodes and transistors, and the parameters of inverter loads, as well as the parasitic nature of semiconductor switches. Second, the state-of-the-art dead-time compensation algorithms are presented in this paper. Third, the advantages and disadvantages of existing algorithms are discussed, together with the future trends of dead-time compensation algorithms. This article provides a complete scenario of dead-time compensation with control strategies for voltage source converters for researchers to identify suitable solutions based on demand and application.
AB - To prevent short-circuits between the upper and lower switches of power converters from over-current protection, the dead time is mandatory in the switching gating signal for voltage source converters. However, this results in many negative effects on system operations, such as output voltage and current distortions (e.g., increased level of fifth and seventh harmonics), zero-current-clamping phenomenon, and output fundamental-frequency voltage reduction. Many solutions have been presented to cope with this problem. First, the dead-time effect is analyzed by taking into account factors such as the zero-clamping phenomenon, voltage drops on diodes and transistors, and the parameters of inverter loads, as well as the parasitic nature of semiconductor switches. Second, the state-of-the-art dead-time compensation algorithms are presented in this paper. Third, the advantages and disadvantages of existing algorithms are discussed, together with the future trends of dead-time compensation algorithms. This article provides a complete scenario of dead-time compensation with control strategies for voltage source converters for researchers to identify suitable solutions based on demand and application.
KW - Dead-time compensation
KW - Harmonics
KW - Power converters
UR - http://www.scopus.com/inward/record.url?scp=85062674574&partnerID=8YFLogxK
U2 - 10.3390/electronics8020196
DO - 10.3390/electronics8020196
M3 - Review article
AN - SCOPUS:85062674574
SN - 2079-9292
VL - 8
JO - Electronics (Switzerland)
JF - Electronics (Switzerland)
IS - 2
M1 - 196
ER -