Abstract
Phase-locked loops (PLLs) are undoubtedly the most popular synchronization technique in power and energy applications. A challenging problem in designing PLLs is the presence of DC offset in their input, which causes fundamental frequency oscillatory errors in their estimated quantities. In this paper, a novel method to tackle this problem is presented. The effectiveness of this approach is verified through numerical results.
Original language | English |
---|---|
Article number | 7439853 |
Journal | IEEE Transactions on Industrial Electronics |
Volume | 63 |
Issue number | 8 |
Pages (from-to) | 4942-4946 |
Number of pages | 5 |
ISSN | 0278-0046 |
DOIs | |
Publication status | Published - Aug 2016 |
Keywords
- Phase locked loops
- Synchronisation