Dual Z-Source Inverter With Three-Level Reduced Common-Mode Switching

Feng Gao, Poh Chiang Loh, Frede Blaabjerg, D.M. Vilathgamuwa

Research output: Contribution to journalJournal articleResearchpeer-review

60 Citations (Scopus)

Abstract

This paper presents the design of a dual Z-source inverter that can be used with either a single dc source or two isolated dc sources. Unlike traditional inverters, the integration of a properly designed Z-source network and semiconductor switches to the proposed dual inverter allows buck-boost power conversion to be performed over a wide modulation range, with three-level output waveforms generated. The connection of an additional transformer to the inverter ac output also allows all generic wye-or delta-connected loads with three-wire or four-wire configuration to be supplied by the inverter. Modulationwise, the dual inverter can be controlled using a carefully designed carrier-based pulsewidth-modulation (PWM) scheme that will always ensure balanced voltage boosting of the Z-source network while simultaneously achieving reduced common-mode switching. Because of the omission of dead-time delays in the dual-inverter PWM scheme, its switched common-mode voltage can be completely eliminated, unlike in traditional inverters, where narrow common-mode spikes are still generated. Under semiconductor failure conditions, the presented PWM schemes can easily be modified to allow the inverter to operate without interruption, and for cases where two isolated sources are used, zero common-mode voltage can still be ensured. These theoretical findings, together with the inverter practicality, have been confirmed in simulations both using PSIM with Matlab/Simulink coupler and experimentally using a laboratory-implemented inverter prototype.
Original languageEnglish
JournalIEEE Transactions on Industry Applications
Volume43
Issue number6
Pages (from-to)1597 - 1608
Number of pages12
ISSN0093-9994
Publication statusPublished - 2007

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