Dynamic Current Sharing Optimization of Asymmetric SiC Power Module

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Abstract

The dynamic current imbalance in the power modules with paralleled Silicon Carbide (SiC) MOSFETs appears due to the die parameter variations and layout asymmetry. This can force the derating of a power module and decrease reliability, potentially leading to a thermal runaway. In this work, an optimization scheme, compensating for the layout asymmetry using the individual gate and drive source resistances is presented. The results are verified experimentally in a Double Pulse Test setup.
Original languageEnglish
Title of host publication2023 IEEE Energy Conversion Congress and Exposition, ECCE 2023
Number of pages5
PublisherIEEE
Publication date29 Oct 2023
Pages5923-5927
Article number10361954
ISBN (Electronic)9798350316445
DOIs
Publication statusPublished - 29 Oct 2023
Event2023 IEEE Energy Conversion Congress and Exposition (ECCE) - Nashville, United States
Duration: 29 Oct 20232 Nov 2023
https://www.ieee-ecce.org/2023/

Conference

Conference2023 IEEE Energy Conversion Congress and Exposition (ECCE)
Country/TerritoryUnited States
CityNashville
Period29/10/202302/11/2023
Internet address

Keywords

  • SiC paralleling
  • current sharing
  • gate resistance
  • optimization

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