Effect of Frequency on Energy Efficient Transceiver Design

Keshav Kumar; Bishwajeet Pandey; Dil Muhammad Akbar Hussain

doi:10.21058/gjet.2019.52002

Effect of Frequency on Energy Efficient Transceiver Design

Keshav Kumar, Bishwajeet Pandey, Dil Muhammad Akbar Hussain

Research output: Contribution to journal › Journal article › Research › peer-review

Abstract

We have observed the different chip power which are clustered on UART device, example IOs, leakage and total power. This through experiment is done at a frequency of 1 GHz, having a duty cycle of 50% and 1ns time period. We did our experiment with Virtex 4, Virtex 5, Virtex 6, Spartan3 and Spartan 6 FPGA. In the experiment we found Spartan 6 uses the least amount of power among all the FPGA used in the experiment.

Original language	English
Journal	Gyancity Journal of Engineering and Technology
Volume	5
Issue number	2
Pages (from-to)	14-18
Number of pages	5
ISSN	2456-0065
DOIs	https://doi.org/10.21058/gjet.2019.52002
Publication status	Published - Jul 2019

Keywords

FPGA
Power
Voltage
UART
Frequency

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10.21058/gjet.2019.52002

http://gjet.gyancity.com/Vol5No2/GJET_Vol5No2_July2019_002.pdf

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title = "Effect of Frequency on Energy Efficient Transceiver Design",

abstract = "We have observed the different chip power which are clustered on UART device, example IOs, leakage and total power. This through experiment is done at a frequency of 1 GHz, having a duty cycle of 50% and 1ns time period. We did our experiment with Virtex 4, Virtex 5, Virtex 6, Spartan3 and Spartan 6 FPGA. In the experiment we found Spartan 6 uses the least amount of power among all the FPGA used in the experiment.",

keywords = "FPGA, Power, Voltage, UART, Frequency",

author = "Keshav Kumar and Bishwajeet Pandey and Hussain, {Dil Muhammad Akbar}",

year = "2019",

month = jul,

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pages = "14--18",

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AU - Kumar, Keshav

AU - Pandey, Bishwajeet

AU - Hussain, Dil Muhammad Akbar

PY - 2019/7

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N2 - We have observed the different chip power which are clustered on UART device, example IOs, leakage and total power. This through experiment is done at a frequency of 1 GHz, having a duty cycle of 50% and 1ns time period. We did our experiment with Virtex 4, Virtex 5, Virtex 6, Spartan3 and Spartan 6 FPGA. In the experiment we found Spartan 6 uses the least amount of power among all the FPGA used in the experiment.

AB - We have observed the different chip power which are clustered on UART device, example IOs, leakage and total power. This through experiment is done at a frequency of 1 GHz, having a duty cycle of 50% and 1ns time period. We did our experiment with Virtex 4, Virtex 5, Virtex 6, Spartan3 and Spartan 6 FPGA. In the experiment we found Spartan 6 uses the least amount of power among all the FPGA used in the experiment.

KW - FPGA

KW - Power

KW - Voltage

KW - UART

KW - Frequency

U2 - 10.21058/gjet.2019.52002

DO - 10.21058/gjet.2019.52002

M3 - Journal article

SN - 2456-0065

VL - 5

SP - 14

EP - 18

JO - Gyancity Journal of Engineering and Technology

JF - Gyancity Journal of Engineering and Technology

IS - 2

ER -

Effect of Frequency on Energy Efficient Transceiver Design

Abstract

Keywords

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