Energy-Aware Scheduling of FIR Filter Structures

In this report we initially introduce four different implementation structures which are suitable for the Finite Impulse Response filters applied in the SDR front-end. We derive data flow graphs and precedence graphs for all four structures using the Synchronous Data Flow (SDF) notation. Using power and timing estimations for addition and multiplication (including idling power consumption) when executed on an Altera Cyclone IV FPGA, we model all the structures in UPPAAL and employ model checking to find energy-optimal solutions in linearly priced timed automata. In conclusion we state that there are significant energy-versus-time differences between the four structures when we experiment with varying numbers of adders and multipliers. Similarly, we found that idling power becomes an important parameter when high numbers of functional units are allocated into the target hardware architecture.