Energy-Aware Scheduling of FIR Filter Structures using a Timed Automata Model

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Abstract

Software Defined Radio (SDR) devices are becoming
increasingly popular due to their support for mode-, standardand
application-flexibility. At the same time however, the energy
consumption of such devices typically suffers from the use of
reconfigurable real-time platforms which are known to be severely
power hungry. In this work we therefore show how to use tools
and techniques developed by the formal methods community to
minimize the energy consumption of Finite Impulse Response
(FIR) filters which are extensively used in SDR front-ends. We
conduct experiments with four different FIR filter structures
where we initially derive data flow graphs and precedence graphs
using the Synchronous Data Flow (SDF) notation. Based on actual
measurements on the Altera Cyclone IV FPGA, we derive power
and timing estimates for addition and multiplication, including
idling power consumption. We next model the FIR structures
in UPPAAL CORA and employ model checking to find energyoptimal
solutions in linearly priced timed automata. In conclusion
we state that there are significant energy-versus-time differences
between the four structures when we experiment with varying
numbers of adders and multipliers. Similarly, we find that idle
power becomes an important parameter when a high number of
functional units are allocated.
Original languageEnglish
Title of host publication2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
Number of pages6
PublisherIEEE
Publication date20 Apr 2016
Pages163-168
ISBN (Electronic)978-1-5090-2466-7
DOIs
Publication statusPublished - 20 Apr 2016
EventInternational Symposium on Design and Diagnostics of Electronic Circuits & Systems - Košice, Slovakia
Duration: 20 Apr 201622 Apr 2016

Conference

ConferenceInternational Symposium on Design and Diagnostics of Electronic Circuits & Systems
CountrySlovakia
CityKošice
Period20/04/201622/04/2016

Cite this

Wognsen, E. R., Hansen, R. R., Larsen, K. G., & Koch, P. (2016). Energy-Aware Scheduling of FIR Filter Structures using a Timed Automata Model. In 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) (pp. 163-168). IEEE. https://doi.org/10.1109/DDECS.2016.7482468
Wognsen, Erik Ramsgaard ; Hansen, Rene Rydhof ; Larsen, Kim Guldstrand ; Koch, Peter. / Energy-Aware Scheduling of FIR Filter Structures using a Timed Automata Model. 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE, 2016. pp. 163-168
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title = "Energy-Aware Scheduling of FIR Filter Structures using a Timed Automata Model",
abstract = "Software Defined Radio (SDR) devices are becomingincreasingly popular due to their support for mode-, standardandapplication-flexibility. At the same time however, the energyconsumption of such devices typically suffers from the use ofreconfigurable real-time platforms which are known to be severelypower hungry. In this work we therefore show how to use toolsand techniques developed by the formal methods community tominimize the energy consumption of Finite Impulse Response(FIR) filters which are extensively used in SDR front-ends. Weconduct experiments with four different FIR filter structureswhere we initially derive data flow graphs and precedence graphsusing the Synchronous Data Flow (SDF) notation. Based on actualmeasurements on the Altera Cyclone IV FPGA, we derive powerand timing estimates for addition and multiplication, includingidling power consumption. We next model the FIR structuresin UPPAAL CORA and employ model checking to find energyoptimalsolutions in linearly priced timed automata. In conclusionwe state that there are significant energy-versus-time differencesbetween the four structures when we experiment with varyingnumbers of adders and multipliers. Similarly, we find that idlepower becomes an important parameter when a high number offunctional units are allocated.",
keywords = "FIR Filter, FPGA, Timed automata, UPPAAL, VHDL, Power Consumption",
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Wognsen, ER, Hansen, RR, Larsen, KG & Koch, P 2016, Energy-Aware Scheduling of FIR Filter Structures using a Timed Automata Model. in 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE, pp. 163-168, International Symposium on Design and Diagnostics of Electronic Circuits & Systems, Košice, Slovakia, 20/04/2016. https://doi.org/10.1109/DDECS.2016.7482468

Energy-Aware Scheduling of FIR Filter Structures using a Timed Automata Model. / Wognsen, Erik Ramsgaard; Hansen, Rene Rydhof; Larsen, Kim Guldstrand; Koch, Peter.

2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE, 2016. p. 163-168.

Research output: Contribution to book/anthology/report/conference proceedingArticle in proceedingResearchpeer-review

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Wognsen ER, Hansen RR, Larsen KG, Koch P. Energy-Aware Scheduling of FIR Filter Structures using a Timed Automata Model. In 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE. 2016. p. 163-168 https://doi.org/10.1109/DDECS.2016.7482468