Fast Electro-thermal Simulation Strategy for SiC MOSFETs Based on Power Loss Mapping

Lorenzo Ceccarelli; Ramchandra Kotecha; Francesco Iannuzzo; Alan Mantooth

doi:10.1109/PEAC.2018.8590288

Fast Electro-thermal Simulation Strategy for SiC MOSFETs Based on Power Loss Mapping

Lorenzo Ceccarelli, Ramchandra Kotecha, Francesco Iannuzzo, Alan Mantooth

Research output: Contribution to book/anthology/report/conference proceeding › Article in proceeding › Research › peer-review

12 Citations (Scopus)

249 Downloads (Pure)

Abstract

A fast electro-thermal simulation strategy for SiC power MOSFETs is presented in this paper. This approach features the detailed mapping of the device power losses under a wide range of operating conditions by using a compact electrical model and its experimental validation for a 1.2 kV/36 A commercial device. The losses condition map is used in the simplified model of a half-bridge inverter topology. The average device losses per switching period are injected into a multi-layer thermal impedance network obtained via finite-element method (FEM) simulation. The strategy allows the electro-thermal simulation of a simple switching pattern in a very short time (seconds), compared to an equivalent physically-based circuit simulation, without significant accuracy loss, enabling long-timescale simulation and reliable, mission-profile oriented design of power electronic converters.

Original language	English
Title of host publication	Proceedings of the 2018 IEEE International Power Electronics and Application Conference and Exposition, PEAC 2018
Number of pages	6
Publisher	IEEE Press
Publication date	Nov 2018
Pages	1-6
Article number	8590288
ISBN (Print)	978-1-5386-6055-3
ISBN (Electronic)	978-1-5386-6054-6
DOIs	https://doi.org/10.1109/PEAC.2018.8590288
Publication status	Published - Nov 2018
Event	2018 IEEE International Power Electronics and Application Conference and Exposition, PEAC 2018 - Shenzhen, China Duration: 4 Nov 2018 → 7 Nov 2018

Conference

Conference	2018 IEEE International Power Electronics and Application Conference and Exposition, PEAC 2018
Country/Territory	China
City	Shenzhen
Period	04/11/2018 → 07/11/2018
Sponsor	China Power Supply Society (CPSS), IEEE Power Electronics Society (PELS)

Keywords

SiC MOSFET
compact model
electro-thermal simulation
power electronics reliability

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10.1109/PEAC.2018.8590288

Final_PEAC_2018_newAccepted author manuscript, 706 KB

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Cite this

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title = "Fast Electro-thermal Simulation Strategy for SiC MOSFETs Based on Power Loss Mapping",

abstract = "A fast electro-thermal simulation strategy for SiC power MOSFETs is presented in this paper. This approach features the detailed mapping of the device power losses under a wide range of operating conditions by using a compact electrical model and its experimental validation for a 1.2 kV/36 A commercial device. The losses condition map is used in the simplified model of a half-bridge inverter topology. The average device losses per switching period are injected into a multi-layer thermal impedance network obtained via finite-element method (FEM) simulation. The strategy allows the electro-thermal simulation of a simple switching pattern in a very short time (seconds), compared to an equivalent physically-based circuit simulation, without significant accuracy loss, enabling long-timescale simulation and reliable, mission-profile oriented design of power electronic converters.",

keywords = "SiC MOSFET, compact model, electro-thermal simulation, power electronics reliability",

author = "Lorenzo Ceccarelli and Ramchandra Kotecha and Francesco Iannuzzo and Alan Mantooth",

year = "2018",

month = nov,

doi = "10.1109/PEAC.2018.8590288",

language = "English",

isbn = "978-1-5386-6055-3",

pages = "1--6",

booktitle = "Proceedings of the 2018 IEEE International Power Electronics and Application Conference and Exposition, PEAC 2018",

publisher = "IEEE Press",

note = "2018 IEEE International Power Electronics and Application Conference and Exposition, PEAC 2018 ; Conference date: 04-11-2018 Through 07-11-2018",

}

Ceccarelli, L, Kotecha, R, Iannuzzo, F & Mantooth, A 2018, Fast Electro-thermal Simulation Strategy for SiC MOSFETs Based on Power Loss Mapping. in Proceedings of the 2018 IEEE International Power Electronics and Application Conference and Exposition, PEAC 2018., 8590288, IEEE Press, pp. 1-6, 2018 IEEE International Power Electronics and Application Conference and Exposition, PEAC 2018, Shenzhen, China, 04/11/2018. https://doi.org/10.1109/PEAC.2018.8590288

Fast Electro-thermal Simulation Strategy for SiC MOSFETs Based on Power Loss Mapping. / Ceccarelli, Lorenzo; Kotecha, Ramchandra; Iannuzzo, Francesco et al.
Proceedings of the 2018 IEEE International Power Electronics and Application Conference and Exposition, PEAC 2018. IEEE Press, 2018. p. 1-6 8590288.

Research output: Contribution to book/anthology/report/conference proceeding › Article in proceeding › Research › peer-review

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T1 - Fast Electro-thermal Simulation Strategy for SiC MOSFETs Based on Power Loss Mapping

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AU - Kotecha, Ramchandra

AU - Iannuzzo, Francesco

AU - Mantooth, Alan

PY - 2018/11

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N2 - A fast electro-thermal simulation strategy for SiC power MOSFETs is presented in this paper. This approach features the detailed mapping of the device power losses under a wide range of operating conditions by using a compact electrical model and its experimental validation for a 1.2 kV/36 A commercial device. The losses condition map is used in the simplified model of a half-bridge inverter topology. The average device losses per switching period are injected into a multi-layer thermal impedance network obtained via finite-element method (FEM) simulation. The strategy allows the electro-thermal simulation of a simple switching pattern in a very short time (seconds), compared to an equivalent physically-based circuit simulation, without significant accuracy loss, enabling long-timescale simulation and reliable, mission-profile oriented design of power electronic converters.

AB - A fast electro-thermal simulation strategy for SiC power MOSFETs is presented in this paper. This approach features the detailed mapping of the device power losses under a wide range of operating conditions by using a compact electrical model and its experimental validation for a 1.2 kV/36 A commercial device. The losses condition map is used in the simplified model of a half-bridge inverter topology. The average device losses per switching period are injected into a multi-layer thermal impedance network obtained via finite-element method (FEM) simulation. The strategy allows the electro-thermal simulation of a simple switching pattern in a very short time (seconds), compared to an equivalent physically-based circuit simulation, without significant accuracy loss, enabling long-timescale simulation and reliable, mission-profile oriented design of power electronic converters.

KW - SiC MOSFET

KW - compact model

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KW - power electronics reliability

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M3 - Article in proceeding

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BT - Proceedings of the 2018 IEEE International Power Electronics and Application Conference and Exposition, PEAC 2018

PB - IEEE Press

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Y2 - 4 November 2018 through 7 November 2018

ER -

Fast Electro-thermal Simulation Strategy for SiC MOSFETs Based on Power Loss Mapping

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