FPGA-based implementation of MMC control based on sorting networks

Mattia Ricco*, Laszlo Mathe, Eric Monmasson, Remus Teodorescu

*Corresponding author for this work

Research output: Contribution to journalJournal articleResearchpeer-review

16 Citations (Scopus)
150 Downloads (Pure)

Abstract

In Modular Multilevel Converter (MMC) applications, the balancing of the capacitor voltages is one of the most important issues for achieving the proper behavior of the MMC. The Capacitor Voltage Balancing (CVB) control is usually based on classical sorting algorithms which consist of repetitive/recursive loops. This leads to an increase of the execution time when many Sub-Modules (SMs) are employed. When the execution time of the balancing is longer than the sampling period, the proper operation of the MMC cannot be ensured. Moreover, due to their inherent sequential operation, sorting algorithms are suitable for software implementation (microcontrollers or DSPs), but they are not appropriate for a hardware implementation. Instead, in this paper, Sorting Networks (SNs) are proposed due to their convenience for implementation in FPGA devices. The advantages and the main challenges of the Bitonic SN in MMC applications are discussed and different FPGA implementations are presented. Simulation results are provided in normal and faulty conditions. Moreover, a comparison with the widely used bubble sorting algorithm and max/min approach is made in terms of execution time and performance. Finally, hardware-in-the-loop results are shown to prove the effectiveness of the implemented SN.
Original languageEnglish
Article number2394
JournalEnergies
Volume11
Issue number9
Pages (from-to)1-18
Number of pages18
ISSN1996-1073
DOIs
Publication statusPublished - Sept 2018

Keywords

  • Capacitor voltage balancing
  • Field-programmable gate array
  • Modular multilevel converters
  • Sorting networks

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