Influences of Device and Circuit Mismatches on Paralleling Silicon Carbide MOSFETs

Helong Li, Stig Munk-Nielsen, Xiongfei Wang, Ram Krishan Maheshwari, Szymon Beczkowski, Christian Uhrenfeldt, Toke Franke

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133 Citations (Scopus)
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Abstract

This paper addresses the influences of device and circuit mismatches on paralleling the Silicon Carbide (SiC) MOSFETs. Comprehensive theoretical analysis and experimental validation from paralleled discrete devices to paralleled dies in multichip power modules are first presented. Then, the influence of circuit mismatch on paralleling SiC MOSFETs is investigated and experimentally evaluated for the first time. It is found that the mismatch of the switching loop stray inductance can also lead to on-state current unbalance with inductive output current, in addition to the on-state resistance of the device. It further reveals that circuit mismatches and a current coupling among the paralleled dies exist in a SiC MOSFET multichip power module, which is critical for the transient current distribution in the power module. Thus, a power module layout with an auxiliary source connection is developed to reduce such a coupling effect. Lastly, simulations and experimental tests are carried out to validate the analysis and effectiveness of the developed layout.
Original languageEnglish
JournalI E E E Transactions on Power Electronics
Volume31
Issue number1
Pages (from-to)621 - 634
Number of pages14
ISSN0885-8993
DOIs
Publication statusPublished - Jan 2016

Keywords

  • DBC layout
  • Parallel Connection
  • Power module
  • SiC MOSFET
  • WBG devices

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