Abstract
This paper gives a layout design principle for multichip SiC MOSFET power modules taking the transient current distribution among paralleled dies into consideration. A few typical power module layouts are analyzed and modeled with parasitic layout parameters. With the analysis and comparison, a universal and practical design principle is proposed, which is to make the direction of parallel connections perpendicular to the direction of current flow. Applying this design principle mitigates the di/dt through the parasitic inductance between the source terminals of the paralleled dies. Furthermore, this approach avoids current coupling effects, which aggravate transient current imbalances. The design principle is verified with experimental results.
| Original language | English |
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| Title of host publication | 2023 25th European Conference on Power Electronics and Applications, EPE 2023 ECCE Europe |
| Publisher | IEEE (Institute of Electrical and Electronics Engineers) |
| Publication date | 2023 |
| ISBN (Electronic) | 9789075815412 |
| DOIs | |
| Publication status | Published - 2023 |
| Externally published | Yes |
| Event | 25th European Conference on Power Electronics and Applications, EPE 2023 ECCE Europe - Aalborg, Denmark Duration: 4 Sept 2023 → 8 Sept 2023 |
Conference
| Conference | 25th European Conference on Power Electronics and Applications, EPE 2023 ECCE Europe |
|---|---|
| Country/Territory | Denmark |
| City | Aalborg |
| Period | 04/09/2023 → 08/09/2023 |
| Series | 2023 25th European Conference on Power Electronics and Applications, EPE 2023 ECCE Europe |
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Bibliographical note
Publisher Copyright:© 2023 EPE Association.
Keywords
- Layout Design
- Multichip Power Module
- Parallel Connection
- SiC MOSFETs