Abstract
The electrical loading and device rating are both important factors that determine the loss and thermal behaviors of power semiconductor devices. In the existing loss and thermal models, only the electrical loadings are focused and treated as design variables, while the device rating is normally pre-defined by experience with poor design flexibility. Consequently a more complete loss and thermal model is proposed in this paper, which takes into account not only the electrical loading but also the device rating as input variables. The quantified correlation between the power loss, thermal impedance and silicon area of Insulated Gate Bipolar Transistor (IGBT) is mathematically established. By this new modeling approach, all factors that have impacts to the loss and thermal profiles of power devices can be accurately mapped, enabling more design freedom to optimize the efficiency and thermal loading of power converter. The proposed model can be further improved by experimental tests, and it is well agreed by both circuit and Finite Element Method (FEM) simulation results.
| Original language | English |
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| Title of host publication | Proceedings of the 2014 International Power Electronics Conference (IPEC-Hiroshima 2014 - ECCE-ASIA) |
| Number of pages | 8 |
| Publisher | IEEE Press |
| Publication date | May 2014 |
| Pages | 2862-2869 |
| ISBN (Print) | 9781479927067 |
| ISBN (Electronic) | 9781479927043 |
| DOIs | |
| Publication status | Published - May 2014 |
| Event | 2014 International Power Electronics Conference (IPEC-Hiroshima 2014 - ECCE-ASIA) - Hiroshima, Japan Duration: 18 May 2014 → 21 May 2014 |
Conference
| Conference | 2014 International Power Electronics Conference (IPEC-Hiroshima 2014 - ECCE-ASIA) |
|---|---|
| Country/Territory | Japan |
| City | Hiroshima |
| Period | 18/05/2014 → 21/05/2014 |