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Abstract
This paper presents a compact model for ${rm P}^{+}$ guard rings in lightly doped CMOS substrates featuring a P-well layer. Simple expressions for the impedances in the model are derived based on a conformal mapping approach. The model can be used to predict the noise suppression performance of ${rm P}^{+}$ guard rings in terms of S-parameters, which is useful for substrate noise mitigation in mixed-signal system-on-chips. Validation of the model has been done by both electromagnetic simulation and experimental results from guard rings implemented using a standard 0.18-$mu{rm m}$ CMOS process. In addition, design guidelines have been drawn for minimizing the guard ring size while maintaining the noise suppression performance.
Original language | English |
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Journal | I E E E Transactions on Electron Devices |
Volume | 60 |
Issue number | 9 |
Pages (from-to) | 2854-2861 |
Number of pages | 8 |
ISSN | 0018-9383 |
DOIs | |
Publication status | Published - Aug 2013 |
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Dive into the research topics of 'Modeling and Design Guidelines for P⁺ Guard Rings in Lightly Doped CMOS Substrates'. Together they form a unique fingerprint.Projects
- 1 Finished
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Microwatt Radio for Self-Sustaining Wireless Sensor Networks
Shen, M. (Project Participant) & Mikkelsen, J. H. (Project Participant)
The Danish Council for Independent Research, Technology and Production Sciences. Individual Post-doc
01/01/2011 → 30/04/2014
Project: Research