Modeling and Design Guidelines for P⁺ Guard Rings in Lightly Doped CMOS Substrates

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Abstract

This paper presents a compact model for ${rm P}^{+}$ guard rings in lightly doped CMOS substrates featuring a P-well layer. Simple expressions for the impedances in the model are derived based on a conformal mapping approach. The model can be used to predict the noise suppression performance of ${rm P}^{+}$ guard rings in terms of S-parameters, which is useful for substrate noise mitigation in mixed-signal system-on-chips. Validation of the model has been done by both electromagnetic simulation and experimental results from guard rings implemented using a standard 0.18-$mu{rm m}$ CMOS process. In addition, design guidelines have been drawn for minimizing the guard ring size while maintaining the noise suppression performance.
Original languageEnglish
JournalI E E E Transactions on Electron Devices
Volume60
Issue number9
Pages (from-to)2854-2861
Number of pages8
ISSN0018-9383
DOIs
Publication statusPublished - Aug 2013

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