Modeling and Design of a 1.2 pF Common-Mode Capacitance Transformer for Powering MV SiC MOSFETs Gate Drivers

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Abstract

This paper proposes a physics-level modeling method for analyzing the primary to secondary-side (common-mode) parasitic capacitance of the transformer for the Medium-voltage SiC MOSFETs gate drivers. The lumped circuit-based physics-model of the turn-to-turn capacitance, turn-to-core capacitance, and self capacitance of the core are derived, and it is found that the turn-to-core capacitance mainly contributes to the total equivalent parasitic common-mode capacitance. The measured common-mode impedance of the transformer shows high agreements with the calculated value, where the accuracy of the proposed modeling method can be proved based on the experimental results.
Original languageEnglish
Title of host publicationProceedings of IECON 2019 - 45th Annual Conference of the IEEE Industrial Electronics Society
Number of pages7
Place of PublicationLisbon, Portugal
PublisherIEEE Press
Publication dateOct 2019
DOIs
Publication statusPublished - Oct 2019
EventIECON 2019 - 45th Annual Conference of the IEEE Industrial Electronics Society - Lisbon, Portugal
Duration: 14 Oct 201917 Oct 2019

Conference

ConferenceIECON 2019 - 45th Annual Conference of the IEEE Industrial Electronics Society
Country/TerritoryPortugal
CityLisbon
Period14/10/201917/10/2019
SeriesProceedings of the Annual Conference of the IEEE Industrial Electronics Society
ISSN1553-572X

Keywords

  • Common-mode capacitance
  • SiC MOSFETs gate drivers
  • Lumped circuit-based physics-level model
  • Turn-to-core capacitance

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