Multi-chip medium voltage SiC MOSFET power module with focus on low parasitic capacitance

Jannick Kjær Jørgensen; Dipen Narendra Dalal; Szymon Beczkowski; Stig Munk-Nielsen; Christian Uhrenfeldt

Multi-chip medium voltage SiC MOSFET power module with focus on low parasitic capacitance

Jannick Kjær Jørgensen, Dipen Narendra Dalal, Szymon Beczkowski, Stig Munk-Nielsen, Christian Uhrenfeldt

Research output: Contribution to book/anthology/report/conference proceeding › Article in proceeding › Research › peer-review

18 Citations (Scopus)

Abstract

Advances in high breakdown voltage SiC MOSFETs is enabling the use of simpler topologies, such as a half-bridge in medium voltage applications. In order to increase the power output it is necessary to parallel multiple MOSFETs, which can be done in power modules. At high voltage operating conditions parasitic capacitances of the power module become increasingly important to consider, due to increased switching losses and increased risk to cause EMI. A 10 kV, 80 A half-bridge design is presented using four MOSFETs in parallel, with a design focus on minimal parasitic capacitances.

Original language	English
Title of host publication	CIPS 2020 - 11th International Conference on Integrated Power Electronics Systems
Number of pages	6
Publisher	VDE Verlag GMBH
Publication date	2020
Pages	154-159
ISBN (Electronic)	9783800752263
Publication status	Published - 2020
Event	11th International Conference on Integrated Power Electronics Systems, CIPS 2020 - Berlin, Germany Duration: 24 Mar 2020 → 26 Mar 2020

Conference

Conference	11th International Conference on Integrated Power Electronics Systems, CIPS 2020
Country/Territory	Germany
City	Berlin
Period	24/03/2020 → 26/03/2020

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@inproceedings{174cd72871424fd19eb0d0519dc85621,

title = "Multi-chip medium voltage SiC MOSFET power module with focus on low parasitic capacitance",

abstract = "Advances in high breakdown voltage SiC MOSFETs is enabling the use of simpler topologies, such as a half-bridge in medium voltage applications. In order to increase the power output it is necessary to parallel multiple MOSFETs, which can be done in power modules. At high voltage operating conditions parasitic capacitances of the power module become increasingly important to consider, due to increased switching losses and increased risk to cause EMI. A 10 kV, 80 A half-bridge design is presented using four MOSFETs in parallel, with a design focus on minimal parasitic capacitances.",

author = "J{\o}rgensen, {Jannick Kj{\ae}r} and Dalal, {Dipen Narendra} and Szymon Beczkowski and Stig Munk-Nielsen and Christian Uhrenfeldt",

note = "Publisher Copyright: {\textcopyright} VDE VERLAG GMBH · Berlin · Offenbach.; 11th International Conference on Integrated Power Electronics Systems, CIPS 2020 ; Conference date: 24-03-2020 Through 26-03-2020",

year = "2020",

language = "English",

pages = "154--159",

booktitle = "CIPS 2020 - 11th International Conference on Integrated Power Electronics Systems",

publisher = "VDE Verlag GMBH",

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Jørgensen, JK, Dalal, DN, Beczkowski, S , Munk-Nielsen, S & Uhrenfeldt, C 2020, Multi-chip medium voltage SiC MOSFET power module with focus on low parasitic capacitance. in CIPS 2020 - 11th International Conference on Integrated Power Electronics Systems. VDE Verlag GMBH, pp. 154-159, 11th International Conference on Integrated Power Electronics Systems, CIPS 2020, Berlin, Germany, 24/03/2020. <https://ieeexplore.ieee.org/document/9097674>

Multi-chip medium voltage SiC MOSFET power module with focus on low parasitic capacitance. / Jørgensen, Jannick Kjær; Dalal, Dipen Narendra; Beczkowski, Szymon et al.
CIPS 2020 - 11th International Conference on Integrated Power Electronics Systems. VDE Verlag GMBH, 2020. p. 154-159.

Research output: Contribution to book/anthology/report/conference proceeding › Article in proceeding › Research › peer-review

TY - GEN

T1 - Multi-chip medium voltage SiC MOSFET power module with focus on low parasitic capacitance

AU - Jørgensen, Jannick Kjær

AU - Dalal, Dipen Narendra

AU - Beczkowski, Szymon

AU - Munk-Nielsen, Stig

AU - Uhrenfeldt, Christian

PY - 2020

Y1 - 2020

N2 - Advances in high breakdown voltage SiC MOSFETs is enabling the use of simpler topologies, such as a half-bridge in medium voltage applications. In order to increase the power output it is necessary to parallel multiple MOSFETs, which can be done in power modules. At high voltage operating conditions parasitic capacitances of the power module become increasingly important to consider, due to increased switching losses and increased risk to cause EMI. A 10 kV, 80 A half-bridge design is presented using four MOSFETs in parallel, with a design focus on minimal parasitic capacitances.

AB - Advances in high breakdown voltage SiC MOSFETs is enabling the use of simpler topologies, such as a half-bridge in medium voltage applications. In order to increase the power output it is necessary to parallel multiple MOSFETs, which can be done in power modules. At high voltage operating conditions parasitic capacitances of the power module become increasingly important to consider, due to increased switching losses and increased risk to cause EMI. A 10 kV, 80 A half-bridge design is presented using four MOSFETs in parallel, with a design focus on minimal parasitic capacitances.

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M3 - Article in proceeding

AN - SCOPUS:85099730898

SP - 154

EP - 159

BT - CIPS 2020 - 11th International Conference on Integrated Power Electronics Systems

PB - VDE Verlag GMBH

T2 - 11th International Conference on Integrated Power Electronics Systems, CIPS 2020

Y2 - 24 March 2020 through 26 March 2020

ER -

Multi-chip medium voltage SiC MOSFET power module with focus on low parasitic capacitance

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