Output impedance design of parallel-connected UPS inverters

Josep M. Guerrero, Luis García De Vicuña, Jose Matas, Jaume Miret, Miguel Castilla

Research output: Contribution to conference without publisher/journalPaper without publisher/journalResearchpeer-review

31 Citations (Scopus)
Original languageEnglish
Publication date1 Dec 2004
Number of pages6
DOIs
Publication statusPublished - 1 Dec 2004
Event2004 IEEE International Symposium on Industrial Electronics, IEEE-ISlE -
Duration: 4 May 20047 May 2004

Conference

Conference2004 IEEE International Symposium on Industrial Electronics, IEEE-ISlE
Period04/05/200407/05/2004

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Keywords

  • Output impedance
  • Parallel operation
  • Uninterruptible power supplies
  • Wireless control.

Cite this

Guerrero, J. M., De Vicuña, L. G., Matas, J., Miret, J., & Castilla, M. (2004). Output impedance design of parallel-connected UPS inverters. 1123-1128. Paper presented at 2004 IEEE International Symposium on Industrial Electronics, IEEE-ISlE, . https://doi.org/10.1109/ISIE.2004.1571971