Power Analysis of Energy Efficient DES Algorithm and Implementation on 28nm FPGA

Vandana  Thind; Bishwajeet Pandey; Dil muhammed Akbar Hussain

doi:10.1109/CSE-EUC-DCABES.2016.247

Power Analysis of Energy Efficient DES Algorithm and Implementation on 28nm FPGA

Vandana Thind, Bishwajeet Pandey, Dil muhammed Akbar Hussain

Research output: Contribution to book/anthology/report/conference proceeding › Article in proceeding › Research › peer-review

3 Citations (Scopus)

415 Downloads (Pure)

Abstract

In this work, we have done power analysis ofData Encryption Standard (DES) algorithm using Xilinx ISE software development kit. We have analyzed the amount of power utilized by selective components on board i.e., FPGA Artix-7, where DES algorithm is implemented. The components taken into consideration areclock power, logic power, signals power, IOs power, leakage powerand supply power (dynamic and quiescent). We have used four different WLAN frequencies (2.4 GHz, 3.6 GHz, 4.9GHz, and 5.9 GHz) and four different IO standards like HSTL-I, HSTL-II, HSTL-II-18, HSTL-I-18 for power analysis. We have achieved13-47% saving in power at different frequencies and withdifferent energy efficient HSTL IO standard. We calculated the percentage change in the IO power with respect to the mean values of IO power at four different frequencies. We notified that there is minimum of -37.5% and maximum of +35.8% variations.This work helps to design and implement DES algorithm with maximum power efficiency.

Original language	English
Title of host publication	Proceedings of the 15th International Symposium on Distributed Computing and Applications to Business, Engineering and Science (DCABES 2016)
Number of pages	4
Place of Publication	Paris, France
Publisher	IEEE Press
Publication date	Aug 2016
Pages	600-603
ISBN (Print)	978-1-5090-3593-9
DOIs	https://doi.org/10.1109/CSE-EUC-DCABES.2016.247
Publication status	Published - Aug 2016
Event	15th International Symposium on Distributed Computing and Applications to Business, Engineering and Science - Paris, France Duration: 24 Aug 2016 → 26 Aug 2016 Conference number: 15 http://dcabes2016.conferences-events.org/

Conference

Conference	15th International Symposium on Distributed Computing and Applications to Business, Engineering and Science
Number	15
Country/Territory	France
City	Paris
Period	24/08/2016 → 26/08/2016
Internet address	http://dcabes2016.conferences-events.org/

Bibliographical note

The proceeding of DCABES2016 will be published by IEEE CPS after the conference. In addition, selected papers will be published in special issues of international journals.

Keywords

XILINX
Clocks Power
Signals Power
IOs Standard
Leakage Power
Supply Power
Maximum Power Efficiency
DES Algorithm
Mean power
Standard deviation

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10.1109/CSE-EUC-DCABES.2016.247

Power Analysis of Energy Efficient DES Algorithm and Implementation on 28nm FPGASubmitted manuscript, 365 KB

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Cite this

@inproceedings{e2ef70530bb54ec3ab36c65502bb0d10,

title = "Power Analysis of Energy Efficient DES Algorithm and Implementation on 28nm FPGA",

abstract = "In this work, we have done power analysis ofData Encryption Standard (DES) algorithm using Xilinx ISE software development kit. We have analyzed the amount of power utilized by selective components on board i.e., FPGA Artix-7, where DES algorithm is implemented. The components taken into consideration areclock power, logic power, signals power, IOs power, leakage powerand supply power (dynamic and quiescent). We have used four different WLAN frequencies (2.4 GHz, 3.6 GHz, 4.9GHz, and 5.9 GHz) and four different IO standards like HSTL-I, HSTL-II, HSTL-II-18, HSTL-I-18 for power analysis. We have achieved13-47% saving in power at different frequencies and withdifferent energy efficient HSTL IO standard. We calculated the percentage change in the IO power with respect to the mean values of IO power at four different frequencies. We notified that there is minimum of -37.5% and maximum of +35.8% variations.This work helps to design and implement DES algorithm with maximum power efficiency. ",

keywords = "XILINX, Clocks Power, Signals Power, IOs Standard, Leakage Power, Supply Power, Maximum Power Efficiency, DES Algorithm, Mean power, Standard deviation",

author = "Vandana Thind and Bishwajeet Pandey and Hussain, {Dil muhammed Akbar}",

note = "The proceeding of DCABES2016 will be published by IEEE CPS after the conference. In addition, selected papers will be published in special issues of international journals. ; 15th International Symposium on Distributed Computing and Applications to Business, Engineering and Science, DCABES 2016 ; Conference date: 24-08-2016 Through 26-08-2016",

year = "2016",

month = aug,

doi = "10.1109/CSE-EUC-DCABES.2016.247",

language = "English",

isbn = "978-1-5090-3593-9",

pages = "600--603",

booktitle = "Proceedings of the 15th International Symposium on Distributed Computing and Applications to Business, Engineering and Science (DCABES 2016)",

publisher = "IEEE Press",

url = "http://dcabes2016.conferences-events.org/",

}

Thind, V, Pandey, B & Hussain, DMA 2016, Power Analysis of Energy Efficient DES Algorithm and Implementation on 28nm FPGA. in Proceedings of the 15th International Symposium on Distributed Computing and Applications to Business, Engineering and Science (DCABES 2016). IEEE Press, Paris, France, pp. 600-603, 15th International Symposium on Distributed Computing and Applications to Business, Engineering and Science, Paris, France, 24/08/2016. https://doi.org/10.1109/CSE-EUC-DCABES.2016.247

Power Analysis of Energy Efficient DES Algorithm and Implementation on 28nm FPGA. / Thind, Vandana ; Pandey, Bishwajeet; Hussain, Dil muhammed Akbar.
Proceedings of the 15th International Symposium on Distributed Computing and Applications to Business, Engineering and Science (DCABES 2016). Paris, France: IEEE Press, 2016. p. 600-603.

Research output: Contribution to book/anthology/report/conference proceeding › Article in proceeding › Research › peer-review

TY - GEN

T1 - Power Analysis of Energy Efficient DES Algorithm and Implementation on 28nm FPGA

AU - Thind, Vandana

AU - Pandey, Bishwajeet

AU - Hussain, Dil muhammed Akbar

N1 - Conference code: 15

PY - 2016/8

Y1 - 2016/8

N2 - In this work, we have done power analysis ofData Encryption Standard (DES) algorithm using Xilinx ISE software development kit. We have analyzed the amount of power utilized by selective components on board i.e., FPGA Artix-7, where DES algorithm is implemented. The components taken into consideration areclock power, logic power, signals power, IOs power, leakage powerand supply power (dynamic and quiescent). We have used four different WLAN frequencies (2.4 GHz, 3.6 GHz, 4.9GHz, and 5.9 GHz) and four different IO standards like HSTL-I, HSTL-II, HSTL-II-18, HSTL-I-18 for power analysis. We have achieved13-47% saving in power at different frequencies and withdifferent energy efficient HSTL IO standard. We calculated the percentage change in the IO power with respect to the mean values of IO power at four different frequencies. We notified that there is minimum of -37.5% and maximum of +35.8% variations.This work helps to design and implement DES algorithm with maximum power efficiency.

AB - In this work, we have done power analysis ofData Encryption Standard (DES) algorithm using Xilinx ISE software development kit. We have analyzed the amount of power utilized by selective components on board i.e., FPGA Artix-7, where DES algorithm is implemented. The components taken into consideration areclock power, logic power, signals power, IOs power, leakage powerand supply power (dynamic and quiescent). We have used four different WLAN frequencies (2.4 GHz, 3.6 GHz, 4.9GHz, and 5.9 GHz) and four different IO standards like HSTL-I, HSTL-II, HSTL-II-18, HSTL-I-18 for power analysis. We have achieved13-47% saving in power at different frequencies and withdifferent energy efficient HSTL IO standard. We calculated the percentage change in the IO power with respect to the mean values of IO power at four different frequencies. We notified that there is minimum of -37.5% and maximum of +35.8% variations.This work helps to design and implement DES algorithm with maximum power efficiency.

KW - XILINX

KW - Clocks Power

KW - Signals Power

KW - IOs Standard

KW - Leakage Power

KW - Supply Power

KW - Maximum Power Efficiency

KW - DES Algorithm

KW - Mean power

KW - Standard deviation

UR - http://dcabes2016.conferences-events.org/files/euc_cse_dcabes_2016.pdf

U2 - 10.1109/CSE-EUC-DCABES.2016.247

DO - 10.1109/CSE-EUC-DCABES.2016.247

M3 - Article in proceeding

SN - 978-1-5090-3593-9

SP - 600

EP - 603

BT - Proceedings of the 15th International Symposium on Distributed Computing and Applications to Business, Engineering and Science (DCABES 2016)

PB - IEEE Press

CY - Paris, France

T2 - 15th International Symposium on Distributed Computing and Applications to Business, Engineering and Science

Y2 - 24 August 2016 through 26 August 2016

ER -

Power Analysis of Energy Efficient DES Algorithm and Implementation on 28nm FPGA

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Bibliographical note

Keywords

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