Reduction of parasitic capacitance in 10 kV SiC MOSFET power modules using 3D FEM

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Abstract

The benefits of emerging wide-band gap semiconductors can only be utilized if the semiconductor is properly packaged. Capacitive coupling in the package causes electromagnetic interference during high dv/dt switching. This paper investigates the current flowing in the parasitic capacitance between the output node and the grounded heat sink for a custom silicon carbide power module. A circuit model of the capacitive coupling path is presented, using parasitic capacitances extracted from ANSYS Q3D. Simulated values are compared with experimental results. A new iteration of the silicon carbide power module is designed, having reduced capacitive coupling without penalizing other parameters. The new module is tested experimentally, which verifies the reduced capacitive coupling to the heat sink.
Original languageEnglish
Title of host publicationProceedings of 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe)
Number of pages8
Place of PublicationWarsaw, Poland
PublisherIEEE Press
Publication dateSep 2017
ISBN (Electronic)978-90-75815-27-6
DOIs
Publication statusPublished - Sep 2017
Event2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe) - Warsaw, Poland
Duration: 11 Sep 201714 Sep 2017

Conference

Conference2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe)
CountryPoland
CityWarsaw
Period11/09/201714/09/2017

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Keywords

  • Packaging
  • Simulation
  • Wide bandgap devices
  • Silicon carbide (SiC)

Cite this

Jørgensen, A. B., Christensen, N., Dalal, D. N., Sønderskov, S. D., Beczkowski, S., Uhrenfeldt, C., & Munk-Nielsen, S. (2017). Reduction of parasitic capacitance in 10 kV SiC MOSFET power modules using 3D FEM. In Proceedings of 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe) IEEE Press. https://doi.org/10.23919/EPE17ECCEEurope.2017.8098962