Reduction of parasitic capacitance in 10 kV SiC MOSFET power modules using 3D FEM

Asger Bjørn Jørgensen; Nicklas Christensen; Dipen Narendra Dalal; Simon Dyhr Sønderskov; Szymon Beczkowski; Christian Uhrenfeldt; Stig Munk-Nielsen

doi:10.23919/EPE17ECCEEurope.2017.8098962

Reduction of parasitic capacitance in 10 kV SiC MOSFET power modules using 3D FEM

Asger Bjørn Jørgensen, Nicklas Christensen, Dipen Narendra Dalal, Simon Dyhr Sønderskov, Szymon Beczkowski, Christian Uhrenfeldt, Stig Munk-Nielsen

Research output: Contribution to book/anthology/report/conference proceeding › Article in proceeding › Research › peer-review

37 Citations (Scopus)

706 Downloads (Pure)

Abstract

The benefits of emerging wide-band gap semiconductors can only be utilized if the semiconductor is properly packaged. Capacitive coupling in the package causes electromagnetic interference during high dv/dt switching. This paper investigates the current flowing in the parasitic capacitance between the output node and the grounded heat sink for a custom silicon carbide power module. A circuit model of the capacitive coupling path is presented, using parasitic capacitances extracted from ANSYS Q3D. Simulated values are compared with experimental results. A new iteration of the silicon carbide power module is designed, having reduced capacitive coupling without penalizing other parameters. The new module is tested experimentally, which verifies the reduced capacitive coupling to the heat sink.

Original language	English
Title of host publication	Proceedings of 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe)
Number of pages	8
Place of Publication	Warsaw, Poland
Publisher	IEEE Press
Publication date	Sept 2017
ISBN (Electronic)	978-90-75815-27-6
DOIs	https://doi.org/10.23919/EPE17ECCEEurope.2017.8098962
Publication status	Published - Sept 2017
Event	2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe) - Warsaw, Poland Duration: 11 Sept 2017 → 14 Sept 2017

Conference

Conference	2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe)
Country/Territory	Poland
City	Warsaw
Period	11/09/2017 → 14/09/2017

Keywords

Packaging
Simulation
Wide bandgap devices
Silicon carbide (SiC)

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10.23919/EPE17ECCEEurope.2017.8098962

epe17_parasiticcapacitance_postprintAccepted author manuscript, 1.07 MB

http://ieeexplore.ieee.org/document/8098962/

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Jørgensen, A. B., Christensen, N., Dalal, D. N., Sønderskov, S. D., Beczkowski, S., Uhrenfeldt, C., & Munk-Nielsen, S. (2017). Reduction of parasitic capacitance in 10 kV SiC MOSFET power modules using 3D FEM. In Proceedings of 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe) IEEE Press. https://doi.org/10.23919/EPE17ECCEEurope.2017.8098962

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title = "Reduction of parasitic capacitance in 10 kV SiC MOSFET power modules using 3D FEM",

abstract = "The benefits of emerging wide-band gap semiconductors can only be utilized if the semiconductor is properly packaged. Capacitive coupling in the package causes electromagnetic interference during high dv/dt switching. This paper investigates the current flowing in the parasitic capacitance between the output node and the grounded heat sink for a custom silicon carbide power module. A circuit model of the capacitive coupling path is presented, using parasitic capacitances extracted from ANSYS Q3D. Simulated values are compared with experimental results. A new iteration of the silicon carbide power module is designed, having reduced capacitive coupling without penalizing other parameters. The new module is tested experimentally, which verifies the reduced capacitive coupling to the heat sink.",

keywords = "Packaging, Simulation, Wide bandgap devices, Silicon carbide (SiC)",

author = "J{\o}rgensen, {Asger Bj{\o}rn} and Nicklas Christensen and Dalal, {Dipen Narendra} and S{\o}nderskov, {Simon Dyhr} and Szymon Beczkowski and Christian Uhrenfeldt and Stig Munk-Nielsen",

year = "2017",

month = sep,

doi = "10.23919/EPE17ECCEEurope.2017.8098962",

language = "English",

booktitle = "Proceedings of 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe)",

publisher = "IEEE Press",

note = "2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe) ; Conference date: 11-09-2017 Through 14-09-2017",

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Jørgensen, AB, Christensen, N, Dalal, DN, Sønderskov, SD, Beczkowski, S, Uhrenfeldt, C & Munk-Nielsen, S 2017, Reduction of parasitic capacitance in 10 kV SiC MOSFET power modules using 3D FEM. in Proceedings of 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe). IEEE Press, Warsaw, Poland, 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe), Warsaw, Poland, 11/09/2017. https://doi.org/10.23919/EPE17ECCEEurope.2017.8098962

Reduction of parasitic capacitance in 10 kV SiC MOSFET power modules using 3D FEM. / Jørgensen, Asger Bjørn; Christensen, Nicklas; Dalal, Dipen Narendra et al.
Proceedings of 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe). Warsaw, Poland: IEEE Press, 2017.

Research output: Contribution to book/anthology/report/conference proceeding › Article in proceeding › Research › peer-review

TY - GEN

T1 - Reduction of parasitic capacitance in 10 kV SiC MOSFET power modules using 3D FEM

AU - Jørgensen, Asger Bjørn

AU - Christensen, Nicklas

AU - Dalal, Dipen Narendra

AU - Sønderskov, Simon Dyhr

AU - Beczkowski, Szymon

AU - Uhrenfeldt, Christian

AU - Munk-Nielsen, Stig

PY - 2017/9

Y1 - 2017/9

N2 - The benefits of emerging wide-band gap semiconductors can only be utilized if the semiconductor is properly packaged. Capacitive coupling in the package causes electromagnetic interference during high dv/dt switching. This paper investigates the current flowing in the parasitic capacitance between the output node and the grounded heat sink for a custom silicon carbide power module. A circuit model of the capacitive coupling path is presented, using parasitic capacitances extracted from ANSYS Q3D. Simulated values are compared with experimental results. A new iteration of the silicon carbide power module is designed, having reduced capacitive coupling without penalizing other parameters. The new module is tested experimentally, which verifies the reduced capacitive coupling to the heat sink.

AB - The benefits of emerging wide-band gap semiconductors can only be utilized if the semiconductor is properly packaged. Capacitive coupling in the package causes electromagnetic interference during high dv/dt switching. This paper investigates the current flowing in the parasitic capacitance between the output node and the grounded heat sink for a custom silicon carbide power module. A circuit model of the capacitive coupling path is presented, using parasitic capacitances extracted from ANSYS Q3D. Simulated values are compared with experimental results. A new iteration of the silicon carbide power module is designed, having reduced capacitive coupling without penalizing other parameters. The new module is tested experimentally, which verifies the reduced capacitive coupling to the heat sink.

KW - Packaging

KW - Simulation

KW - Wide bandgap devices

KW - Silicon carbide (SiC)

U2 - 10.23919/EPE17ECCEEurope.2017.8098962

DO - 10.23919/EPE17ECCEEurope.2017.8098962

M3 - Article in proceeding

BT - Proceedings of 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe)

PB - IEEE Press

CY - Warsaw, Poland

T2 - 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe)

Y2 - 11 September 2017 through 14 September 2017

ER -

Reduction of parasitic capacitance in 10 kV SiC MOSFET power modules using 3D FEM

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