TY - JOUR
T1 - Space-Vector PWM with Common-Mode Voltage Elimination for Multiphase Drives
AU - Lopez, Oscar
AU - Alvarez, Jacobo
AU - Malvar, Jano
AU - Yepes, Alejandro G.
AU - Vidal, Ana
AU - Baneira, Fernando
AU - Perez-Estevez, Diego
AU - Freijedo Fernandez, Francisco Daniel
AU - Doval-Gandoy, Jesus
PY - 2016/12
Y1 - 2016/12
N2 - Switching common-mode voltage (CMV) generated by the pulse width modulation (PWM) of the inverter causes common-mode currents, which lead to motor bearing failures and electromagnetic interference problems in multiphase drives. Such switching CMV can be reduced by taking advantage of the switching states of multilevel multiphase inverters that produce zero CMV. Specific space-vector PWM (SVPWM) techniques with CMV elimination, which only use zero CMV states, have been proposed for three-level five-phase drives, and for open-end winding five-, six-, and seven-phase drives, but such methods cannot be extended to a higher number of levels or phases. This paper presents a general (for any number of levels and phases) SVPMW with CMV elimination. The proposed technique can be applied to most multilevel topologies, has low computational complexity and is suitable for low-cost hardware implementations. The new algorithm is implemented in a low-cost field-programmable gate array and it is successfully tested in the laboratory using a five-level five-phase motor drive.
AB - Switching common-mode voltage (CMV) generated by the pulse width modulation (PWM) of the inverter causes common-mode currents, which lead to motor bearing failures and electromagnetic interference problems in multiphase drives. Such switching CMV can be reduced by taking advantage of the switching states of multilevel multiphase inverters that produce zero CMV. Specific space-vector PWM (SVPWM) techniques with CMV elimination, which only use zero CMV states, have been proposed for three-level five-phase drives, and for open-end winding five-, six-, and seven-phase drives, but such methods cannot be extended to a higher number of levels or phases. This paper presents a general (for any number of levels and phases) SVPMW with CMV elimination. The proposed technique can be applied to most multilevel topologies, has low computational complexity and is suitable for low-cost hardware implementations. The new algorithm is implemented in a low-cost field-programmable gate array and it is successfully tested in the laboratory using a five-level five-phase motor drive.
KW - Common-mode voltage elimination
KW - Field-programmable gate array (FPGA)
KW - Multiphase drive
KW - Space-vector pulse width modulation (PWM)
KW - Voltage source inverter (VSI)
UR - http://www.scopus.com/inward/record.url?scp=84978658341&partnerID=8YFLogxK
U2 - 10.1109/TPEL.2016.2521330
DO - 10.1109/TPEL.2016.2521330
M3 - Journal article
AN - SCOPUS:84978658341
SN - 0885-8993
VL - 31
SP - 8151
EP - 8161
JO - IEEE Transactions on Power Electronics
JF - IEEE Transactions on Power Electronics
IS - 12
M1 - 7390099
ER -