Switching current imbalance mitigation in power modules with parallel connected SiC MOSFETs

Research output: Contribution to book/anthology/report/conference proceedingArticle in proceedingResearchpeer-review

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Abstract

Multichip power modules use parallel connected chips to achieve high current rating. Due to a finite flexibility in a DBC layout, some electrical asymmetries will occur in the module. Parallel connected transistors will exhibit uneven static and dynamic current sharing due to these asymmetries. Especially important are the couplings between gate and power loops of individual transistors. Fast changing source currents cause gate voltage imbalances yielding uneven switching currents. Equalizing gate voltages seen by paralleled transistors, done by adjusting source bond wires, is proposed in this paper. Analysis is performed on an industry standard DBC layout using numerically extracted module parasitics. The method of tuning individual source inductances shows clear improvement in dynamic current balancing and prevents excessive current overshoot during transistors turn-on.
Original languageEnglish
Title of host publicationProceedings of 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe)
Number of pages8
PublisherIEEE Press
Publication dateSep 2017
ISBN (Electronic)978-90-75815-27-6
DOIs
Publication statusPublished - Sep 2017
Event2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe) - Warsaw, Poland
Duration: 11 Sep 201714 Sep 2017

Conference

Conference2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe)
Country/TerritoryPoland
CityWarsaw
Period11/09/201714/09/2017

Keywords

  • Packaging
  • Power semiconductor device
  • Silicon carbide (SiC)
  • Parallel operation

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