Abstract
This poster presentation outlines a proposed framework for handling mapping of signal processing
applications to heterogeneous reconfigurable architectures. The methodology consists of an
extension to traditional multi-processor scheduling by creating a separate HW track for generation
of groups of tasks that are handled similarly to SW processes in a traditional multi-processor
scheduling context.
applications to heterogeneous reconfigurable architectures. The methodology consists of an
extension to traditional multi-processor scheduling by creating a separate HW track for generation
of groups of tasks that are handled similarly to SW processes in a traditional multi-processor
scheduling context.
Original language | English |
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Publication date | 2008 |
Publication status | Published - 2008 |
Event | HiPEAC Advanced Computer Architectures and Compilation for Embedded Systems Summer School - L'Aquila, Italy Duration: 13 Jul 2008 → 19 Jul 2008 Conference number: 4 |
Conference
Conference | HiPEAC Advanced Computer Architectures and Compilation for Embedded Systems Summer School |
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Number | 4 |
Country/Territory | Italy |
City | L'Aquila |
Period | 13/07/2008 → 19/07/2008 |
Keywords
- Reconfigurable Computing
- Heterogeneous Architectures
- Temporal Partitioning
- Binding
- Scheduling