Abstract
In this paper, an experimental study is proposed to investigate the failure effects in IGBT large-area devices due to hard gate driving strategies. Thanks to quasi-3D simulations, a large overcurrent is predicted in few cells and corresponds to a large spike in the gate voltage during collector voltage transient, which is able to trigger the device instability. An interpretation of the phenomenon is given that attributes such spike to a strong current imbalance on the large area device, so that a latch-up failure mechanism is proposed.
Original language | English |
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Journal | Microelectronics Reliability |
Volume | 54 |
Issue number | 9-10 |
Pages (from-to) | 1927-1934 |
Number of pages | 8 |
ISSN | 0026-2714 |
DOIs | |
Publication status | Published - 1 Jan 2014 |
Externally published | Yes |
Keywords
- Gate driving
- IGBT
- Instabilities
- Reliability