Voltage Scalling Based Traffic Light Controller Design on Virtex-7 FPGA Family

Sujeet Pandey, Bhagwan Das, Dil muhammed Akbar Hussain

Research output: Contribution to journalJournal articleResearchpeer-review

Abstract

This is an apporach to design of energy efficient traffic light controller on Virtex-7 FPGA that consume low amount of power. There is a reduction of 46.31%, 70.11% and 82.58% in leakage power as the voltage is scale down from 1.8V to 1.6V, 1.4V and 1.2V respectively at ambient temperature 25oC.There is a reduction of 52.48%, 75.59% and 86.96% in leakage power as the voltage is scale down from 1.8V to 1.6V, 1.4V and 1.2V respectively at ambient temperature 50oC. There is a reduction of 46.31%, 70.11% and 82.58% in clock power as the voltage is scale down from 1.8V to 1.6V, 1.4V and 1.2V respectively at any value of ambient temperature.
Original languageEnglish
JournalGyancity Journal of Engineering and Technology
Volume4
Issue number1
Pages (from-to)31-38
Number of pages8
ISSN2456-0065
DOIs
Publication statusPublished - Jan 2018

Keywords

  • Verilog
  • FPGA
  • Energy Efficient design
  • Traffic Light Controller

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