Voltage Scalling Based Traffic Light Controller Design on Virtex-7 FPGA Family

Sujeet Pandey; Bhagwan Das; Dil muhammed Akbar Hussain

doi:10.21058/gjet.2018.41004

Voltage Scalling Based Traffic Light Controller Design on Virtex-7 FPGA Family

Sujeet Pandey, Bhagwan Das, Dil muhammed Akbar Hussain

Research output: Contribution to journal › Journal article › Research › peer-review

Abstract

This is an apporach to design of energy efficient traffic light controller on Virtex-7 FPGA that consume low amount of power. There is a reduction of 46.31%, 70.11% and 82.58% in leakage power as the voltage is scale down from 1.8V to 1.6V, 1.4V and 1.2V respectively at ambient temperature 25oC.There is a reduction of 52.48%, 75.59% and 86.96% in leakage power as the voltage is scale down from 1.8V to 1.6V, 1.4V and 1.2V respectively at ambient temperature 50oC. There is a reduction of 46.31%, 70.11% and 82.58% in clock power as the voltage is scale down from 1.8V to 1.6V, 1.4V and 1.2V respectively at any value of ambient temperature.

Original language	English
Journal	Gyancity Journal of Engineering and Technology
Volume	4
Issue number	1
Pages (from-to)	31-38
Number of pages	8
ISSN	2456-0065
DOIs	https://doi.org/10.21058/gjet.2018.41004
Publication status	Published - Jan 2018

Keywords

Verilog
FPGA
Energy Efficient design
Traffic Light Controller

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10.21058/gjet.2018.41004

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@article{311c4d4df62445d8aa259914f519ee5c,

title = "Voltage Scalling Based Traffic Light Controller Design on Virtex-7 FPGA Family",

abstract = "This is an apporach to design of energy efficient traffic light controller on Virtex-7 FPGA that consume low amount of power. There is a reduction of 46.31%, 70.11% and 82.58% in leakage power as the voltage is scale down from 1.8V to 1.6V, 1.4V and 1.2V respectively at ambient temperature 25oC.There is a reduction of 52.48%, 75.59% and 86.96% in leakage power as the voltage is scale down from 1.8V to 1.6V, 1.4V and 1.2V respectively at ambient temperature 50oC. There is a reduction of 46.31%, 70.11% and 82.58% in clock power as the voltage is scale down from 1.8V to 1.6V, 1.4V and 1.2V respectively at any value of ambient temperature.",

keywords = "Verilog, FPGA, Energy Efficient design, Traffic Light Controller",

author = "Sujeet Pandey and Bhagwan Das and Hussain, {Dil muhammed Akbar}",

year = "2018",

month = jan,

doi = "10.21058/gjet.2018.41004",

language = "English",

volume = "4",

pages = "31--38",

journal = "Gyancity Journal of Engineering and Technology",

issn = "2456-0065",

number = "1",

}

TY - JOUR

T1 - Voltage Scalling Based Traffic Light Controller Design on Virtex-7 FPGA Family

AU - Pandey, Sujeet

AU - Das, Bhagwan

AU - Hussain, Dil muhammed Akbar

PY - 2018/1

Y1 - 2018/1

N2 - This is an apporach to design of energy efficient traffic light controller on Virtex-7 FPGA that consume low amount of power. There is a reduction of 46.31%, 70.11% and 82.58% in leakage power as the voltage is scale down from 1.8V to 1.6V, 1.4V and 1.2V respectively at ambient temperature 25oC.There is a reduction of 52.48%, 75.59% and 86.96% in leakage power as the voltage is scale down from 1.8V to 1.6V, 1.4V and 1.2V respectively at ambient temperature 50oC. There is a reduction of 46.31%, 70.11% and 82.58% in clock power as the voltage is scale down from 1.8V to 1.6V, 1.4V and 1.2V respectively at any value of ambient temperature.

AB - This is an apporach to design of energy efficient traffic light controller on Virtex-7 FPGA that consume low amount of power. There is a reduction of 46.31%, 70.11% and 82.58% in leakage power as the voltage is scale down from 1.8V to 1.6V, 1.4V and 1.2V respectively at ambient temperature 25oC.There is a reduction of 52.48%, 75.59% and 86.96% in leakage power as the voltage is scale down from 1.8V to 1.6V, 1.4V and 1.2V respectively at ambient temperature 50oC. There is a reduction of 46.31%, 70.11% and 82.58% in clock power as the voltage is scale down from 1.8V to 1.6V, 1.4V and 1.2V respectively at any value of ambient temperature.

KW - Verilog

KW - FPGA

KW - Energy Efficient design

KW - Traffic Light Controller

U2 - 10.21058/gjet.2018.41004

DO - 10.21058/gjet.2018.41004

M3 - Journal article

SN - 2456-0065

VL - 4

SP - 31

EP - 38

JO - Gyancity Journal of Engineering and Technology

JF - Gyancity Journal of Engineering and Technology

IS - 1

ER -

Voltage Scalling Based Traffic Light Controller Design on Virtex-7 FPGA Family

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