Projects per year
Abstract
Timing anomalies make worst-case execution time analysis much harder, because the analysis will have to consider all local choices. It has been widely recognised that certain hardware features are timing anomalous, while others are not. However, defining formally what a timing anomaly is, has been difficult.
We examine previous definitions of timing anomalies, and identify examples where they do not align with common observations. We then provide a definition for consistently slower hardware traces that can be used to define timing anomalies and aligns with common observations.
We examine previous definitions of timing anomalies, and identify examples where they do not align with common observations. We then provide a definition for consistently slower hardware traces that can be used to define timing anomalies and aligns with common observations.
Original language | Danish |
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Title of host publication | Proceedings of the 12th International Workshop on Worst-Case Execution-Time Analysis |
Editors | Tullio Vardanega |
Number of pages | 12 |
Volume | 23 |
Place of Publication | Dagstuhl, Germany |
Publisher | Schloss Dagstuhl. Leibniz-Zentrum für Informatik |
Publication date | 2012 |
Pages | 1-12 |
ISBN (Electronic) | 978-3-939897-41-5 |
DOIs | |
Publication status | Published - 2012 |
Event | International Workshop on Worst-Case Execution Time Analysis - Pisa, Italy Duration: 10 Jul 2012 → 10 Jul 2012 Conference number: 12 |
Conference
Conference | International Workshop on Worst-Case Execution Time Analysis |
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Number | 12 |
Country/Territory | Italy |
City | Pisa |
Period | 10/07/2012 → 10/07/2012 |
Series | OpenAccess Series in Informatics |
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ISSN | 2190-6807 |
Projects
- 1 Finished
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CJ4ES: Certifiable Java for Embedded Systems
Hansen, R. R., Ravn, A. P. & Larsen, K. G.
Forskningsrådet for Teknologi og Produktion
01/03/2011 → 28/02/2014
Project: Research