Generalized diamond-type single DC-source switched-capacitor based multilevel inverter with step-up and natural voltage balancing capabilities

This paper proposes a diamond-shaped high step-up switched-capacitor based basic multilevel inverter topology. The basic switched-capacitor (SC) stage consists of 2 active switches, 2 diodes, and 2 capacitors. Using a single DC source with the unfolding circuit (10 switches, 5 capacitors, and 5 diodes) results in the production of 17 voltage-steps at the output with the gain of up to 8 times of the input voltage. By extending the diamond-shaped switched-capacitor stages, higher voltage levels and voltage gains can be possible. The suggested topology employs two half-bridges (instead of a full-bridge) to produce positive, zero, and negative steps, which reduces the Voltage Stress (VS) on two output switches and consequently reduces Total Voltage Stress (TVS). In addition, the natural voltage balancing of capacitors eliminates the need to an additional control circuitry and consequently reduces the total converter size, complexity, and cost. In addition, modularity, scalability, low voltage ripple on capacitors, low total voltage stress, high power quality, and capability of

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INTRODUCTION
In recent years, multilevel inverters have gained tremendous attention among power electronic converters due to their outstanding features such as: simple structure, suitability for medium/high voltage/power applications, low electromagnetic interference, low total harmonic distortion (THD), and improved power quality [1][2][3].The DC supplies as well as switches and diodes are included devices of multilevel inverters.But numerous devices are demanded for reaching increased steps.In literature, many structures have been presented profiting from the reduced number of devices [4][5][6].The reduction in semiconductor device count leads to reduced gate-driver circuits and reduced overall size and cost [7].Usually, the DC sources are bulkier, heavier, and more expensive than other parts in multilevel inverters.So, most of the papers have focused on presenting structures with less number of DC supplies [8].
The topologies presented in [9, 11, 13-19, 21, 23, 24, 27] are modular and can be extended by increment of switchedcapacitor stages, where the non-modular structures presented in [10,12,20,22] can only be extended by cascading the basic units.This increases the number of sources/devices, weight, cost, and volume of the converter.The extension of [14-19, 23, 24, 27] increases the number of steps and voltage gain, but in [9-13, 20, 22] the voltage gain remains constant.
The SCBMLIs presented in [9,[28][29][30] employ an H-bridge unit to provide negative steps, which imposes maximum voltage stress ( = V o,max ) and consequently high losses on H-bridge switches.To overcome this shortcoming, two half-bridges [11-15, 22-24, 27] or a developed H-bridge [10,[16][17][18][19] can be applied (instead of H-bridge) to create negative steps, where only two switches (instead of 4 switches) are imposed to maximum voltage stress.The creation of AC voltage waveform can be free of H-bridge, developed H-bridge or half-bridges.For example, the bipolar output voltage waveform generation of [21] is accomplished inherently, which reduces the total voltage stress.The SCBMLIs presented in [19][20][21][22][23][24] have been investigated in detail, in the comparison section.
Another important feature in SCBMLIs is the quality of output voltage waveform.Higher number of steps leads to higher quality and lower THDs.However, this objective can be obtained in expense of increased devices, cost, weight, and volume.So, there should be a trade-off between number of devices (cost) and number of steps.While the cost factor is dominant, a linear relationship is preferred between number of levels and devices [20][21][22][23][24].But if quality factor is the main objective, an exponential relation between number of steps and devices is aimed [19], where large number of steps and accordingly high quality and low THD can be achieved.
This paper suggests a modular developed diamondtype single-source SCBMLI configuration that benefits from increased levels per device.Application of 2 half-bridges (for creating negative steps) has reduced the total voltage stress.The suggested topology is extended by adding switched-capacitor stages to reach more steps and higher voltage gains.Also, the suggested structure can properly supply the R-L loads.In Sections 2 and 3, the proposed basic and generalized topologies have been introduced.Then, the modulation technique as well as losses analysis and design procedure of capacitors have been explained in Sections 4 and 5.The comparative analysis is also presented in Section 6.The experimental results and conclusions have been presented in Sections 7 and 8, respectively.

PROPOSED DEVELOPED 17-LEVEL TOPOLOGY
The proposed 17-level configuration (shown in Figure 1) is consisted of a single DC-source, 10 switches, 5 capacitors, and 5 diodes.All the switches are unidirectional.So, the count of switches (N Switch ), MOSFETs (N MOSFET ), and gate-driver circuits (N Driver ) are the same.Thus,   1).Similarly, the C 3 is paralleled with series The process takes place during 9 modes (at zero (  2), during initial cycles.Then, the proposed topology reaches to its steady-state operation.
Figure 3 shows equivalent circuits of the proposed converter during the generation of different voltage steps.It is evident from Figure 3 that the proposed topology can simultaneously produce the output voltage level and balance the charge of capacitors at desired values, which is called "natural voltage balancing".
The voltage stress and Normalized Voltage Stress (NVS) on semiconductors are shown in Table 2.Note that the NVS is defined as voltage stress on semiconductor divided by maximum output voltage: NVS = (VS/V o,max ).The suggested basic topology applies two half-bridges instead of a full-bridge, which keeps the switch count the same, but decreases the voltage stress on H 2 and H 4 switches to quarter.Accordingly, the losses and expense of H 2 , H 4 as well as total voltage stress of the converter are reduced.Only H 1 , and H 3 withstand V o,max .As seen

PROPOSED GENERALIZED TOPOLOGY
The proposed basic topology can be extended by increasing switched-capacitor stages to obtain more voltage gains and output steps, as shown in Figure 4.Each switched-capacitor stage contains 2 unidirectional switches (MOSFETs), 2 capacitors, and 2 diodes.The addition of each switched-capacitor stage doubles positive and negative steps, which improves the output voltage quality and reduces the THD of the suggested topology.Then, the filter can be eliminated or downsized.Also, the voltage gain is doubled by increment of each switched-capacitor stage.
The number of steps and devices, as well as gain of generalized configuration, have been summarized in Table 3, where 'n' denotes the number of switched-capacitor stages.

SWITCHING TECHNIQUE
In this study, the "Nearest Level" (or named as "fundamental frequency") technique has been employed as modulation strategy.In this technique, a sinusoidal waveform with fundamental frequency of 50 Hz is considered as the reference waveform The magnitude of reference waveform can be selected through 0 ≤ V m ≤ N P = (N Level − 1)/2, where N P denotes the total number of positive levels.To guarantee maximum number of levels, the V m should be selected as close as possible to N P .In proposed 17-level topology, the N P is equal to 8. Therefore, the reference waveform is defined as in Equation (4): In nearest level modulation technique, the reference waveform is compared with producible voltage levels (0, ±V IN , ±2V IN ,..., ±8V IN ).At each instant (t), the difference between producible voltage levels and reference waveform (called "error") is monitored.The nearest level to the reference waveform is specified by checking relevant error values.The level that has an error less than 0.5 is the nearest one to the reference waveform.So, it is produced at the output port.While the difference between reference waveform and produced level is less than 0.5, the switching pattern remains unchanged.But, when the error reaches its peak value (error max = 0.5), the switching pattern is changed to produce the next step, as shown in Figure 5 [20].
The step-changing instant of ith voltage level (t i ) can be calculated from Equation (5).Note that Equation ( 5) presents the step-changing times of first quarter of switching cycle.The step-changing instants of 2nd, 3rd and 4th quarters can also be calculated based on symmetric nature of output voltage waveform.As seen from Table 4, the employment of nearest level technique reduces the operating frequency of semiconductors, which leads to suppressed switching losses.The simplicity as well as ease of implementation of nearest level technique has increased its popularity.
To certify low-frequency operation of switches in nearest level technique, the total ON-OFF transitions of switches during each switching cycle have been presented in noted that the H 1 and H 3 switches operate at fundamental frequency, while the other semiconductors operate at quite low switching frequencies.This leads to reduced switching losses.

Losses analysis
The losses occurred in switched-capacitor multilevel inverters can be classified to three main types, which are elaborated in the following.

Conduction losses
The conduction losses usually happen at on-state resistance of switches and diodes (R on ), forward voltage drop of diodes (V FD ) and equivalent series resistance of capacitors (R ESR ).Total conduction losses of the structure can be achieved from (6), where the I rms and I ave denotes the Root Mean Square (RMS) and average values of components' current, respectively [24].

Switching losses
The switching losses happen during ON-OFF transitions of semiconductors.The switching losses depends on voltage stress (V S ) and current stress (I Stress ), rising time (t r ) and falling time (t f ) and switching frequency (f s ) of semiconductors, as (7).In this study, the employment of nearest level modulation technique has reduced the switching frequency of switches, which suppress the switching losses [24].

Voltage ripple loss of capacitors
Besides the conduction losses that happen at ESR of capacitors, the voltage ripple of capacitors is another source of loss, which is called "voltage ripple loss" of capacitors.This kind of loss can be computed from ( 8), where f s : switching frequency, C: capacitance of capacitor, ΔV Ripple : voltage ripple of capacitor [24].

Capacitor design
The voltage ripple of capacitors is an important factor that affects the capacitor losses as well as output voltage quality (and THD).The long discharging intervals of capacitors lead to higher ripples, higher losses and lower output voltage quality.The voltage ripple on capacitors can be limited by suitable design of capacitances.In this paper, the capacitances have been selected based on (9-10) [24], where I o : magnitude of the output current, cos(φ): load power factor, [t start − t end ]: longest discharging interval of capacitors, ΔV Ripple : maximum allowable voltage ripple of capacitors
Table 5 and Figure 6 show the comparison results.Based on Figure 6a, despite using single DC source, the suggested and [19,21,24] topologies produce more steps (or gains) than others.This leads to a compact, cheap, and light structure.Also, to achieve equal steps, the proposed configuration requires less switches, MOSFETs and gate driver circuits than others (see Figure 6b,c).This property leads to reduced size and simple structure.As evident from Figure 7a,b, in wide range, the proposed configuration requires less number of capacitors and diodes than [20][21][22][23][24] to obtain equal number of steps.The reduction in diodes count will lead to reduced losses and improved efficiency.
Figure 8a,b confirms that with the same count of devices (N Source + N MOSFET + N Driver + N Capacitor + N Diode ), the suggested structure can provide more steps and gains than the others.In the other words, to obtain the same gain or steps, the proposed topology requires fewer devices, which causes to have a compact, light, and cheap structure.9, while producing the same gains, less total voltage stress is imposed on semiconductors of proposed topology than other structures.This leads to reduced losses and improved efficiencies.Figure 10 displays the CF/N Level of the proposed topology and [19][20][21][22][23][24] for different weighting coefficient of total voltage stress (α).It is seen that the CF/N Level in the proposed topology is always less than that of other structures, which is a sign of reduced devices, low total voltage stress on semiconductors, and increased number of levels.
Table 5 presents the reported efficiency of topologies presented in [19][20][21][22][23][24] at their operation point (at a specific output power).It is seen that the proposed topology has better efficiency than other counter parts at equal output power levels.Also, the proposed topology has the second least THD among selected topologies.The low-THD of proposed topology is because of its high number of levels.

EXPERIMENTAL RESULTS
To certify the feasibility of the proposed topology, the laboratory-scale prototype of the basic (17-level) structure has been implemented (Figure 11a).The nearest level technique (Figure 5) and the Atmega32 microcontroller have been employed for producing switching pulses.The setup parameters and device specifications have been presented in Table 6.
Figure 11b shows the output voltage/current of the proposed basic topology for R-L load of R = 48 Ω and L = 120 mH.It  Figure 12 shows the dynamic performance of the proposed topology.It is observed that during load step-change from R = 100 Ω to R = 200 Ω, the load current is decreased to about half, and the output voltage increases just 2% to 2.5%.This certifies the appropriate dynamic performance of the proposed topology.
The voltage/current waveforms of C 1 -C 5 have been presented in Figure 13.The results show that the voltage of C 1 -C 5 has been naturally regulated on  The obtained results for voltage ripple of capacitors are Δv C1 ≈ 1 V, Δv C2 = Δv C3 ≈ 1.2 V, and Δv C4 = Δv C5 ≈ 1.6 V.These small values obtained for voltage ripple confirm proper natural voltage balancing of capacitors.Also, the voltage/current waveform of capacitors (Figure 13) indicates that the charge/discharge process of capacitors has been uniformly distributed in the switching period.Based on Table 1, the charge/discharge process of C 2 (or C 4 ) is exactly the same as C 3 (or C 5 ).The only difference is that the C 2 (or C 4 ) is employed in positive voltage levels, but the C 3 (or C 5 ) is applied at the same negative voltage levels.So, the C 2 (or C 4 ) can be selected iden-tical to C 3 (or C 5 ).That is why the voltage waveform, voltage ripple, and charge/discharge current waveform of C 2 (or C 4 ) is similar to that of C 3 (or C 5 ).
The voltage waveform and voltage stress on semiconductors are shown in Figure 14 and Table 7. Figure 14 confirms that only H 1 and H 3 switches withstand V o,max and the voltage stress on other semiconductors (especially the H 1 and H 3 as output switches) are much less than V o,max .
Figure 15 displays the THD of the proposed structure at different modulation indexes.According to Figure 15, as the modulation index increases, the THD of converter decreases, which   Figure 17 shows the loss distribution (in watt and per cent) between switches, diodes, and capacitors at different output powers.
At low powers, the diodes and switches have almost the same losses.But as the output power increases, the loss of diodes becomes larger than that of switches.It is also seen from Figure 17 that the power dissipated in capacitors (due to their voltage ripple) smoothly increases by increment of output power.

CONCLUSIONS
This paper proposes and developed a basic SCBMLI topology that can produce 17 steps and the voltage gain of 8 by means of only 1 DC source, 10 unidirectional switches, 5 capacitors, and 5 diodes.The proposed basic structure can be extended by extending the switched-capacitor stages to achieve higher voltage gains and levels.Due to the single-source nature of the proposed extended topology, it is expected to have less size, weight, and cost than other multi-source counterparts.The proposed generalized topology applies two half-bridges instead of a full-bridge (H-bridge) to create negative steps.Thus, only 2 switches (rather than 4 switches) are imposed to maximum voltage stress.This leads to less total voltage stress.Also, modularity, self-voltage balancing of capacitors, low voltage ripple on capacitors, and suitability for R-L loads are other main advantages of the proposed topology.Due to high quality and low THD of output voltage, the output filter can be eliminated or downsized.It is also noticed from comparison results that the proposed topology has higher steps per device count, higher gain per device count, lower total voltage stress, and lower cost function than other similar SCBMLIs, which are impressive profits.The laboratory-scale prototype of the proposed 17-level topology has been implemented.The comparative analysis as well as experimental results certify the effective and correct performance of the suggested topology.

FIGURE 1
FIGURE 1 Proposed 17-level inverter topology IN and −4V IN voltage levels) at each switching cycle.Similarly, the C 5 is paralleled with series connection of V IN , C 1 and C 2 , through S 1 , S 2 , S 3 , D 3 and D 5 .So, it is charged to V C5 = V IN + V C1 + V C2 = 4V IN .The charging process of C 5 happens in 9 operational modes (while generation of zero (I o ≥ 0), +1V IN , +2V IN , +3V IN , +4V IN , −5V IN , −6V IN , −7V IN and −8V IN voltage levels).Due to numerous charging modes of C 1 -C 5 capacitors, the voltage of capacitors is naturally balanced on desired values presented in Equation (

FIGURE 3
FIGURE 3 Operational modes of proposed 17-level converter

FIGURE 4
FIGURE 4 Proposed extended topology

FIGURE 6
FIGURE 6 Comparison results for number of sources, switches, gate-driver circuits and MOSFETs: (a) N Level vs. N Source ; (b) N Level vs. N Switch and N Driver ; (c) N Level vs. N MOSFET

FIGURE 7 FIGURE 8 FIGURE 9
FIGURE 7 Comparative analysis on number of levels, capacitors and diodes: (a) N Level vs. N Capacitor ; (b) N Level vs. N Diode

Capacitances C 1 =FIGURE 11
FIGURE 11 Experimental setup and results: (a) laboratory prototype of proposed 17-level topology; (b) output voltage and current waveforms; (c) harmonic spectrum

FIGURE 12 FIGURE 13
FIGURE 12 Dynamic performance of proposed topology during load step change from 113 to 60 W

FIGURE 14
FIGURE 14 Voltage waveforms of (a) diodes and (b) switches Figure 16a shows the measured efficiency of suggested 17level structure for different pure resistive loads of R = 210[Ω]

FIGURE 16 FIGURE 17
FIGURE 16 Efficiency analysis: (a) efficiency of proposed basic topology at pure resistive loads; (b) power losses at operating point (R = 48 Ω and L = 120 mH)

S 1 S 2 S 3 P 1 P 2 P 3 H 1 H 2 H 3 H 4 D 1 D 2 D 3 D 4 D 5 C 1 C 2 C 3 C 4 C 5
±5V IN and ±7V IN voltage levels.This guarantees the voltage balancing of C 1 to V IN (V C1 = V IN ).The C 2 capacitor is paralleled with series connection of V IN and C 1 , through S 1 , P 2 and D 2 .So, the C 2 is charged to V C2 = V IN +V C1 = 2V IN .The charging of C 2 occurs during 5 intervals at each cycle, while generation of zero (I o < 0), +4V IN , +8V IN , −2V IN and −6V IN voltage levels (Table

TABLE 2
Voltage stress (VS) on switches/diodes of proposed 17-level topology

TABLE 3
Description of proposed generalized topology

Table 4 .
It isFIGURE 5 Nearest-level based switching pattern of suggested 17-level topology

TABLE 4
ON/OFF transitions of switches at each switching period and estimated operating frequency of switches

TABLE 5
Comparison statistics

TABLE 6
Description of the experimental setup

TABLE 7
Experimental results obtained for voltage stress (VS) on switches/diodes 15GURE15THD of the output voltage vs. modulation index leads to higher qualities.Note that at low modulation indexes, the number of levels of proposed topology decreases, but it still operates as a multilevel inverter.