Virtual-Flux-Based Passivation of Current Control for Grid-Connected VSCs

This letter proposes a passivity-based current control (CC) scheme for voltage-source converters, featuring a virtual-flux-based damper and a passive output admittance with a wide range of time delay involved in the CC loop. The admittance modeling and experimental tests validate the effectiveness of the approach.


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Abstract-This letter proposes a passivity-based current control scheme for voltage-source converters, featuring a virtual-flux-based damper and a passive output admittance with a wide range of time delay involved in the current control loop.The admittance modeling and experimental tests validate the effectiveness of the approach.

I.INTRODUCTION
The harmonic stability caused by the dynamic interactions of voltage-source converters (VSCs) and the electrical grid is threatening the security of electricity supply [1].The varying topologies and conditions of power systems further challenge the analysis and mitigation of harmonic instability [2].
The passivity-based control of VSCs recently emerges as a promising way to tackle the instability challenge [3].The concept of passivity in the frequency domain implies that the real part of the output admittance of VSC, i.e.YVSC, is nonnegative [4], which ensures that VSC will not destabilize the power system [5].It has been recently found that the highfrequency (e.g. from 200 Hz up to the Nyquist frequency) characteristic of YVSC is dominated by the current control (CC) loop [3], and the time delay involved in the CC loop is identified as the main cause for the negative-real-part of YVSC in the high frequency range [5]- [7].
Considering that the time delay is typically one and a half sampling period (1.5Ts) in digital control systems [8], several active damping schemes have been developed to minimize the negative-real-part region [5]- [6].However, only the method reported in [5] can ensure the nonnegative real part of YVSC up to the Nyquist frequency, yet it requires the use of a voltage derivative term (namely dev_AD) in the voltage feedforward loop, which is sensitive to high-frequency noise.Moreover, the time delay in the control of modular multilevel converters and, particularly in the high-voltage direct-current systems, can be much longer than 1.5Ts, ranging from 3Ts to 6Ts, due to the complexity in the control of thousands of submodules [9].As will be revealed in this letter, the dev_AD method fails to ensure the passivity of YVSC when the delay is longer than 1.5Ts.
To address the passivity of the CC loop with a wide range of time delay, a virtual-flux-based active damping (VF_AD) method is proposed in this letter.The approach is easy to implement and fully removes time delay terms in YVSC, which guarantees its passivity with any time delay in the CC loop.The small-signal modeling and experimental tests are presented, which corroborate the effectiveness of the proposed method.

II.PASSIVITY-BASED ANALYSIS OF CURRENT CONTROL
A. Grid-Connected Voltage-Source Converter Fig. 1(a) shows the single-line diagram of a grid-connected three-phase VSC with the CC implemented in the αβ-frame.Lf is the filter inductor and Zg represents the grid impedance.vPCC and iPCC are the voltage and current at the point of common coupling (PCC) of VSC, respectively.idqref and iαβref are current references in the dq-and αβ-frame, respectively.The CC loop is used to control the output current of VSC (which is equal to iPCC) to follow its reference.Since the focus of this letter is the passivity of the CC loop, the phase-locked loop (PLL) is designed with a low bandwidth to avoid the low-frequency instability [1], and a constant dc-link voltage can also be assumed, which is justified by: 1) The dc-link voltage is controlled by the direct voltage control (DVC) loop to generate idref.The bandwidth of the DVC is usually well below the fundamental frequency [3].Hence, the dc-link voltage ripple is attenuated by the DVC and will not be reflected in idref.
2) The dc-link voltage ripple compensation is usually adopted in the pulse width modulation (PWM) [10], with which, the dc-link voltage ripple would not affect the dynamics of the ac voltage and current of VSC [10].
where H(s) is the closed-loop transfer function between iαβref and iPCCαβ, and YVSC(s) is the output admittance of VSC with the CC loop.
It is known from [5] that the stability of VSCs connected with the passive grid impedance can be guaranteed if 1) H(s) is stable, and 2) YVSC(s) is passive.While 1) can be easily guaranteed by properly tuning the PR controller parameters, the passivity of YVSC(s) required by 2) is hard to achieve, due to the impact of the time delay, which will be detailed in the following part.The main circuit and controller parameters used in the following analysis and experimental tests are given in Table I.

1) With PR controller only
First, only the current controller without the active damping, i.e.Gv(s)=0, is considered.Since the R controller is merely designed to eliminate the steady-state current tracking error at the grid fundamental frequency, it can be neglected when analyzing the high-frequency characteristic of YVSC [6].Hence, Gi(s) can be simplified as the proportional gain, i.e., ≈ Kp.Consequently, YVSC(s) can be simplified as: Substituting 's = jω' into (2), the real part of YVSC(s), i.e.Re{YVSC(jω)} can be obtained as Since the denominator of (3) is always larger than zero, the sign of Re{YVSC(jω)} is determined by the numerator.The frequency range of the negative-real-part region can be obtained by solving < 0, which leads to _ 0.25 0.75 , ,  For Td =1.5Ts, the frequency range of the single negativereal-part region within the Nyquist frequency is obtained by substituting n=0 into (4), which leads to ∈(fs/6, fs/2) [5]- [7].
2) PR controller plus dev_AD dev_AD scheme reported in [5] is used to eliminate the negative-real-part region.By selecting Gv(s) =Kads, Re{YVSC(jω)} is expressed as where Kad = 4Td 2 Kp/(π 2 Lf).The term (Kp-ω 2 KadLf) in the numerator becomes negative at the same frequency as the term cos(ωTd), i.e. ω=π/(2Td), which removes the 1 st negative-realpart region in Fig. 2   and hence, are not considered in [5].Yet, they are within the Nyquist frequency if the time delay in the CC loop is longer than 1.5Ts.Fig. 3 illustrates Re{YVSC(jω)} with Td=3.5Ts.It is clear that the additional negative-real-part region is introduced even though the 1 st negative-real-part region in Fig. 2 is eliminated.

A. General Idea
It can be observed from (1) that the delay terms appear both in the numerator and denominator of YVSC(s), which can be cancelled out with each other by selecting Gv(s) = -Kp/(sLf), i.e.,

 
  Since the integral of the PCC voltage leads to the virtual flux (VF) [11], the proposed method is here named as VF_AD.It is known from (6) that the VF_AD scheme fully eliminates the of the time The output admittance of VSC with the CC loop is shaped as the filter reactance, and is always passive.
Remark 1: After using the proposed VF_AD, the antivoltage disturbance capability of VSC is solely determined by the passive filter, and is decoupled from the proportional gain of the current controller.To further improve the harmonic voltage disturbance rejection capability of VSC, the additional harmonic controllers/filters need to be added in the current controller as well as the PCC voltage-feedforward loop.The relevant research works can be found in [12]- [13], where the harmonic controllers/filters need to be properly tuned to avoid jeopardizing the passivity of the CC loop [12]- [13].
Remark 2: YVSC(s) with the dq-frame CC can be obtained from (1) by applying the frequency translation, i.e., s→s-jωg, to Gi(s) [14].However, the high-frequency negative-real-part of YVSC(s) is mainly determined by the proportional gain of Gi(s), which is not affected by the frequency translation [5].Hence, the proposed VF_AD can also be implemented in the dq-frame CC by adding the active damping term after the dq to αβ transformation of the CC output.

B. Practical Implementation
Several modifications are required for implementing the VF_AD scheme in practice.First, the integrator in Gv(s) introduces a high gain at the fundamental frequency, which affects the current tracking performance.This side effect can be avoided by adding a notch filter in Gv(s), which is expressed as where ωg represents the grid fundamental frequency, ωc = π rad/s is selected to guarantee the adaptation of Gnotch(s) to the variation of ωg in the range of ±0.5 Hz.It is worth mentioning that the notch filter only affects system dynamics around the fundamental frequency, and thus, has little impact on the highfrequency characteristic of YVSC.
Second, the voltage sensor may have a small dc offset, and it can lead to a large dc bias in the VF due to the infinite dc gain of the pure integrator in Gv(s), which finally causes the malfunction of VSC [11].The typical solution is the use of a low pass filter (LPF) 1/(s+ωf) to mimic the pure integrator 1/s while avoiding its infinite dc gain, where ωf is the cut-off frequency of the LPF.The smaller ωf yields better emulation of the integrator, but worsen the dynamic performance.Hence, a tradeoff is needed for selecting ωf.It is known from (4) that the delay-induced negative-real-part region starts from fcritical =1/(4Td).In order to guarantee a good approximation of the integrator in the frequency range beyond ωf =0.05•(2πfcritical) is selected in this letter.Hence, the practical implementation of Gv(s) is modified as Fig. 4 shows a comparison of Re{YVSC(jω)} with different control schemes.It can be clearly observed that the negativereal-part region is fully eliminated by using the ideal VF_AD given by ( 6).Yet, a negative-real-part region still remains with the filtered VF_AD given by ( 8), due to the adoption of the LPF instead of the pure integrator in Gv(s), as the zoom-in figure shown in Fig. 4. Nevertheless, the magnitude of the negative Re{YVSC(jω)} is significantly reduced by using the filtered VF_AD compared with the existing methods (i.e., the PR controller only and the controller plus dev_AD).In practice, such a small negative damping of VSC is usually mitigated by the parasitic resistance of the passive-network, and hence, will not destabilize the system [7].

C. Robustness Analysis
It is known from (8) that implementing the filtered VF_AD requires the knowledge of Lf, whose actual value (Lf_actual) might have ±10% deviation from its nominal value (Lf_nominal) due to the component tolerance [15].Fig. 5 shows a comparison of Re{YVSC(jω)} with the filtered VF_AD by considering ±10% variations of Lf.It can be seen that the negative-real-part regions are changed when Lf_actual ≠ Lf_nominal, but their magnitudes are still much smaller compared with the case where the VF_AD is not used, as the blue and black dash-dotted lines shown in Fig. 5. Therefore, the proposed VF_AD performs robustly in keeping a small negative Re{YVSC(jω)} against filter inductance variations.

IV.EXPERIMENTAL RESULTS
To verify the effectiveness of the proposed method.The experimental tests are carried out by using a VSC with parameters in Table I.The grid impedance is represented by the CL filter, with which, the grid resonance frequency can be tuned by changing the grid capacitance Cg and grid inductance Lg.
Fig. 6 (a) plots output admittances of VSC with different control schemes and the grid admittance with Lg= 6 mH and Cg=10μF.It can be seen that the grid admittance intersects VSC admittance in its negative-real-part region if only the PR controller is used in the CC loop, which leads to -10° phase margin (PM).Hence, the system will be unstable.Nevertheless, the system can still be stabilized by adding the dev_AD and the VF_AD.These theoretical analyses are further verified by experimental tests shown in Fig. 7. To avoid the possible damage, the VSC will be blocked in the experiment if the oscillation is amplified, as shown in Fig. 7(a).
Fig. 6 (b) plots output admittances of VSC with different control schemes and the grid admittance with Lg= 6 mH and Cg=4μF.Due to the reduced grid capacitance, the grid admittance intersects with VSC admittance at the higher frequency, which falls into its negative-real-part region if only the PR controller, or PR controller plus dev_AD is used in the CC loop.Therefore, VSC will be unstable with these two control schemes.Yet, VSC can still be stabilized by using the proposed VF_AD, thanks to the widened nonnegative-real-part region.These stability analyses are further verified by the experimental tests given by Fig. 8.

V.CONCLUSION
This letter has proposed a virtual-flux-based active damping that fully eliminates the destabilization effect of the time delay in the current control loop.The output admittance of VSC is shaped as the passive reactance by using the proposed method, with which, the stability robustness of VSC with a wide range of grid impedance is enhanced.The experimental tests are carried out to corroborate the effectiveness of the proposed method.

Fig. 1 (
b) illustrates the block diagram of the used αβ-frame CC.Gi(s) denotes the proportional + resonant (PR) current controller.Gd(s) represents the transfer function of the time delay, i.e., Gd(s)=e -sTd , where Td is the time delay [3].Gv(s) is the active damping controller based on the feedforward of the PCC voltage.Based on Fig.1(b), the output current of VSC can be expressed as[5]