TY - JOUR
T1 - Research On Variable-Length Transfer Delay and Delayed-Signal-Cancellation-Based PLLs
AU - Golestan, Saeed
AU - Guerrero, Josep M.
AU - Quintero, Juan Carlos Vasquez
AU - Abusorrah, Abdullah M.
AU - Al-Turki, Yusuf
PY - 2018/10
Y1 - 2018/10
N2 - In power and energy applications, implementing a large number of phase-locked loops (PLLs) involves using transfer delays. These delays are employed for different control and filtering purposes, such as creating a fictitious orthogonal signal (which is required for the frame transformation in singlephase PLLs) and filtering harmonics, dc offset, and other disturbances. Depending on the application in hand and the expected variation range of the grid frequency, the length of these delays may be variable or fixed. Roughly speaking, the variablelength delays are often preferred for applications where large frequency drifts are anticipated and a high accuracy is required. To the best of authors' knowledge, the small-signal modeling of a variable-length delay-based PLL has not yet been conducted. The main aim of this paper is to cover this gap. The tuning procedure and analysis of these PLLs are then presented. As design examples, some well-known single-phase and three-phase PLLs are considered.
AB - In power and energy applications, implementing a large number of phase-locked loops (PLLs) involves using transfer delays. These delays are employed for different control and filtering purposes, such as creating a fictitious orthogonal signal (which is required for the frame transformation in singlephase PLLs) and filtering harmonics, dc offset, and other disturbances. Depending on the application in hand and the expected variation range of the grid frequency, the length of these delays may be variable or fixed. Roughly speaking, the variablelength delays are often preferred for applications where large frequency drifts are anticipated and a high accuracy is required. To the best of authors' knowledge, the small-signal modeling of a variable-length delay-based PLL has not yet been conducted. The main aim of this paper is to cover this gap. The tuning procedure and analysis of these PLLs are then presented. As design examples, some well-known single-phase and three-phase PLLs are considered.
KW - Delayed signal cancelation
KW - Orthogonal signal
KW - Phase-locked loop (PLL)
KW - Single-phase systems
KW - Synchronization
KW - Three-phase systems
KW - Transfer delay
UR - http://www.scopus.com/inward/record.url?scp=85039779865&partnerID=8YFLogxK
U2 - 10.1109/TPEL.2017.2785281
DO - 10.1109/TPEL.2017.2785281
M3 - Journal article
SN - 0885-8993
VL - 33
SP - 8388
EP - 8398
JO - I E E E Transactions on Power Electronics
JF - I E E E Transactions on Power Electronics
IS - 10
ER -