A Temperature-Dependent dVCE/dt model for Field-Stop IGBT at Turn-off Transient

Peng Xue*, Pooya Davari

*Corresponding author for this work

Research output: Contribution to journalJournal articleResearchpeer-review

1 Citation (Scopus)
108 Downloads (Pure)

Abstract

In this article, an analytical model is proposed to model collector-emitter voltage rising slope (dVCEdt) of field-stop insulated gate bipolar transistor (FS IGBT) during the turn-off transient. Thanks to TCAD simulation, the internal physics of the FS IGBT during VCE rise transient is investigated. Based on the improved understanding of the VCE rise transient, an analytical solution of the excess carrier distribution in the N-base region and field-stop (FS) layer is derived. An analytical model for dVCE/dt of FS IGBT is also proposed. The temperature dependency of various silicon material and device parameters is included in the model. In the end, the double-pulse tests are performed on 650-V/40-A and 1200-V/40-A FS IGBTs. The test results are compared with the analytical predictions and good agreement is obtained.

Original languageEnglish
JournalI E E E Journal of Emerging and Selected Topics in Power Electronics
Volume11
Issue number3
Pages (from-to)3173-3183
Number of pages11
ISSN2168-6777
DOIs
Publication statusPublished - 1 Jun 2023

Keywords

  • Analytical models
  • Capacitance
  • Charge carrier density
  • Germanium
  • IGBT modeling
  • Insulated gate bipolar transistors
  • Logic gates
  • Transient analysis
  • collector-emitter voltage rising slope
  • field-stop (FS) IGBT
  • turn-off transient

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