Frequency Scaling and High Speed Transceiver Logic Based Low Power UART design on 45nm FPGA

UART is a trendy two-wire communication interface. It recognized as Universal Asynchronous Receiver Transmitter. It is an important element to communicate two microcontroller based system. It is widely used in case if high-speed transmission is not required. The main aim to implement the UART on 45nm technology based Spartan-6 FPGA and achieve reliable, compact and stable data transmission. In order to make the more energy efficient UART we have used the HSTL (High-Speed Transceiver Logic) IO standards. To achieve speed and high performance of UART, we have preferred HSTL (High-Speed Transceiver Logic) IOSTANDARD. In this paper, we have used HSTL-II, HSTL-II-18, HSTL-III, and HSTL-III-18. We have also used Frequency Scaling techniques, so we can analyze the demand of different power by device at different frequencies. We have analyzed the demand of total power of different IO Standard at different frequency level so then we make UART more energy efficient. Our analysis has explained that the main reason for power consumption in UART with above IO standard are Clock and IO powers, which we have analyzed at different frequencies.