A ZVS PWM control strategy with balanced capacitor current for half-bridge three-level DC/DC converter

Research output: Contribution to book/anthology/report/conference proceedingArticle in proceedingResearchpeer-review

Abstract

The capacitor current would be imbalanced under the conventional control strategy in the half-bridge three-level (HBTL) DC/DC converter due to the effect of the output inductance of the power supply and the input line inductance, which would affect the converter's reliability. This paper proposes a pulse-wide modulation (PWM) strategy composed of two operation modes for the HBTL DC/DC converter, which can realize the zero-voltage switching (ZVS) for the efficiency improvement. In addition, a capacitor current balancing control is proposed by alternating the two operation modes of the proposed ZVS PWM strategy, which can eliminate the current imbalance among the two input capacitors. Therefore, the proposed control strategy can improve the converter's performance and reliability in: 1) reducing the switching losses and noises of the power switches; 2) balancing the thermal stresses and lifetimes among the two input capacitors. Finally, the simulation and experimental results are presented to verify the proposed control strategy.
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Details

The capacitor current would be imbalanced under the conventional control strategy in the half-bridge three-level (HBTL) DC/DC converter due to the effect of the output inductance of the power supply and the input line inductance, which would affect the converter's reliability. This paper proposes a pulse-wide modulation (PWM) strategy composed of two operation modes for the HBTL DC/DC converter, which can realize the zero-voltage switching (ZVS) for the efficiency improvement. In addition, a capacitor current balancing control is proposed by alternating the two operation modes of the proposed ZVS PWM strategy, which can eliminate the current imbalance among the two input capacitors. Therefore, the proposed control strategy can improve the converter's performance and reliability in: 1) reducing the switching losses and noises of the power switches; 2) balancing the thermal stresses and lifetimes among the two input capacitors. Finally, the simulation and experimental results are presented to verify the proposed control strategy.
Original languageEnglish
Title of host publicationProceedings of the 2017 IEEE Applied Power Electronics Conference and Exposition (APEC)
Number of pages8
PublisherIEEE Press
Publication dateMar 2017
Pages307-314
Article number7930710
ISBN (Electronic)978-1-5090-5366-7
DOI
StatePublished - Mar 2017
Publication categoryResearch
Peer-reviewedYes
Event2017 IEEE Applied Power Electronics Conference and Exposition (APEC) - Tampa Convention Center, Tampa, FL, United States
Duration: 26 Mar 201730 Mar 2017

Conference

Conference2017 IEEE Applied Power Electronics Conference and Exposition (APEC)
LocationTampa Convention Center
LandUnited States
ByTampa, FL
Periode26/03/201730/03/2017

    Research areas

  • Capacitor current balance, DC/DC three-level converter, Zero-voltage-switching (ZVS)
ID: 260306105