Role of parasitic capacitances in power MOSFET turn-on switching speed limits: A SiC case study

Davide Cittanti; Francesco Iannuzzo; Eckart Hoene; Kirill Klein

doi:10.1109/ECCE.2017.8095952

Role of parasitic capacitances in power MOSFET turn-on switching speed limits: A SiC case study

Davide Cittanti, Francesco Iannuzzo, Eckart Hoene, Kirill Klein

Research output: Contribution to book/anthology/report/conference proceeding › Article in proceeding › Research › peer-review

29 Citations (Scopus)

Abstract

This paper describes the effect of MOSFET internal capacitances on the channel current during the turn-on switching transition: an intrinsic theoretical switching speed limit is found and detailed mathematically. The set of analytical equations is solved and the effect of the displacement currents is highlighted with ideal simulated waveforms. A laboratory experiment is thus performed, in order to prove the theoretical predictions: a 25 mΩ SiC CREE power MOSFET is turned on in a no-load condition (zero drain current), starting from different drain-source voltage values. Finally, a LTSpice equivalent circuit model is also built, to better simulate the experimental behavior of the device, adding circuit strain components and other non-idealities to the overall model. A good match between measurements and simulations is observed, mostly validating either the theoretical assumptions and the presented model.

Original language	English
Title of host publication	Proceedings of 2017 IEEE Energy Conversion Congress and Exposition (ECCE)
Publisher	IEEE Press
Publication date	Oct 2017
ISBN (Electronic)	978-1-5090-2998-3
DOIs	https://doi.org/10.1109/ECCE.2017.8095952
Publication status	Published - Oct 2017
Event	2017 IEEE Energy Conversion Congress and Exposition (ECCE) - Cincinnati, Ohio, United States Duration: 1 Oct 2017 → 5 Oct 2017

Conference

Conference	2017 IEEE Energy Conversion Congress and Exposition (ECCE)
Country/Territory	United States
City	Cincinnati, Ohio
Period	01/10/2017 → 05/10/2017

Keywords

Power MOSFET
Switching losses
Turn on
MOSFET parasitic capacitances
SiC MOSFET

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10.1109/ECCE.2017.8095952

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@inproceedings{7ac83062f34241c09ab343e039382689,

title = "Role of parasitic capacitances in power MOSFET turn-on switching speed limits: A SiC case study",

abstract = "This paper describes the effect of MOSFET internal capacitances on the channel current during the turn-on switching transition: an intrinsic theoretical switching speed limit is found and detailed mathematically. The set of analytical equations is solved and the effect of the displacement currents is highlighted with ideal simulated waveforms. A laboratory experiment is thus performed, in order to prove the theoretical predictions: a 25 mΩ SiC CREE power MOSFET is turned on in a no-load condition (zero drain current), starting from different drain-source voltage values. Finally, a LTSpice equivalent circuit model is also built, to better simulate the experimental behavior of the device, adding circuit strain components and other non-idealities to the overall model. A good match between measurements and simulations is observed, mostly validating either the theoretical assumptions and the presented model.",

keywords = "Power MOSFET, Switching losses, Turn on, MOSFET parasitic capacitances, SiC MOSFET",

author = "Davide Cittanti and Francesco Iannuzzo and Eckart Hoene and Kirill Klein",

year = "2017",

month = oct,

doi = "10.1109/ECCE.2017.8095952",

language = "English",

booktitle = "Proceedings of 2017 IEEE Energy Conversion Congress and Exposition (ECCE)",

publisher = "IEEE Press",

note = "2017 IEEE Energy Conversion Congress and Exposition (ECCE) ; Conference date: 01-10-2017 Through 05-10-2017",

}

Cittanti, D, Iannuzzo, F, Hoene, E & Klein, K 2017, Role of parasitic capacitances in power MOSFET turn-on switching speed limits: A SiC case study. in Proceedings of 2017 IEEE Energy Conversion Congress and Exposition (ECCE). IEEE Press, 2017 IEEE Energy Conversion Congress and Exposition (ECCE), Cincinnati, Ohio, United States, 01/10/2017. https://doi.org/10.1109/ECCE.2017.8095952

Role of parasitic capacitances in power MOSFET turn-on switching speed limits: A SiC case study. / Cittanti, Davide; Iannuzzo, Francesco; Hoene, Eckart et al.
Proceedings of 2017 IEEE Energy Conversion Congress and Exposition (ECCE). IEEE Press, 2017.

Research output: Contribution to book/anthology/report/conference proceeding › Article in proceeding › Research › peer-review

TY - GEN

T1 - Role of parasitic capacitances in power MOSFET turn-on switching speed limits

T2 - 2017 IEEE Energy Conversion Congress and Exposition (ECCE)

AU - Cittanti, Davide

AU - Iannuzzo, Francesco

AU - Hoene, Eckart

AU - Klein, Kirill

PY - 2017/10

Y1 - 2017/10

N2 - This paper describes the effect of MOSFET internal capacitances on the channel current during the turn-on switching transition: an intrinsic theoretical switching speed limit is found and detailed mathematically. The set of analytical equations is solved and the effect of the displacement currents is highlighted with ideal simulated waveforms. A laboratory experiment is thus performed, in order to prove the theoretical predictions: a 25 mΩ SiC CREE power MOSFET is turned on in a no-load condition (zero drain current), starting from different drain-source voltage values. Finally, a LTSpice equivalent circuit model is also built, to better simulate the experimental behavior of the device, adding circuit strain components and other non-idealities to the overall model. A good match between measurements and simulations is observed, mostly validating either the theoretical assumptions and the presented model.

AB - This paper describes the effect of MOSFET internal capacitances on the channel current during the turn-on switching transition: an intrinsic theoretical switching speed limit is found and detailed mathematically. The set of analytical equations is solved and the effect of the displacement currents is highlighted with ideal simulated waveforms. A laboratory experiment is thus performed, in order to prove the theoretical predictions: a 25 mΩ SiC CREE power MOSFET is turned on in a no-load condition (zero drain current), starting from different drain-source voltage values. Finally, a LTSpice equivalent circuit model is also built, to better simulate the experimental behavior of the device, adding circuit strain components and other non-idealities to the overall model. A good match between measurements and simulations is observed, mostly validating either the theoretical assumptions and the presented model.

KW - Power MOSFET

KW - Switching losses

KW - Turn on

KW - MOSFET parasitic capacitances

KW - SiC MOSFET

U2 - 10.1109/ECCE.2017.8095952

DO - 10.1109/ECCE.2017.8095952

M3 - Article in proceeding

BT - Proceedings of 2017 IEEE Energy Conversion Congress and Exposition (ECCE)

PB - IEEE Press

Y2 - 1 October 2017 through 5 October 2017

ER -

Role of parasitic capacitances in power MOSFET turn-on switching speed limits: A SiC case study

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Keywords

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