Abstract
This paper presents how the tool TetaSARTS can be used to support the development of embedded hard real-time systems written in Java using the emerging Safety Critical Java (SCJ) profile. TetaSARTS facilitates control-flow sensitive schedulability analysis of a set of real-time tasks, and features a pluggable platform specification allowing analysis of systems including the hosting execution environment. This is achieved by approaching the analysis as a model checking problem by modelling the system using the Timed Automata formalism of the model checking tool Uppaal. The resulting Timed Automata model facilitates easy adjustment of a wide variety of parameters that may be of interest such as processor frequency.
This paper demonstrates that TetaSARTS can be used for tuning processor frequency, for conducting control-flow sensitive Worst Case Response Time analysis, and for conducting processor utilisation and idle time analysis.
This paper demonstrates that TetaSARTS can be used for tuning processor frequency, for conducting control-flow sensitive Worst Case Response Time analysis, and for conducting processor utilisation and idle time analysis.
| Original language | English |
|---|---|
| Journal | WiP Proceedings of the 19th IEEE Real-Time and Embedded Technology and Applications Symposium |
| Pages (from-to) | 41-44 |
| Number of pages | 4 |
| Publication status | Published - 2013 |
| Event | 19th IEEE Real-Time and Embedded Technology and Applications Symposium - Hyatt Regency Philadelphia at Penn's Landing, Philadelphia, Pennsylvania, United States Duration: 10 Apr 2013 → 11 Apr 2013 Conference number: 19 http://www.cister.isep.ipp.pt/rtas2013/ |
Conference
| Conference | 19th IEEE Real-Time and Embedded Technology and Applications Symposium |
|---|---|
| Number | 19 |
| Location | Hyatt Regency Philadelphia at Penn's Landing |
| Country/Territory | United States |
| City | Philadelphia, Pennsylvania |
| Period | 10/04/2013 → 11/04/2013 |
| Internet address |