Abstract
The dc component, which may be caused by different factors in the grid voltage, is one of the disturbances that may severely affect the performance of grid synchronization systems and, therefore, grid-tied power converters. In the phase-locked loop (PLL) and frequency-locked loop (FLL)-based grid synchronization systems, which this article focuses on, some solutions to deal with this challenge have been proposed in the literature. One of the best available solutions is adding dc rejection/estimation loop(s) to a standard PLL and FLL structure. This approach provides an estimation of the dc component and, at the same time, makes the PLL and FLL immune to disturbance effects of the dc component. Despite their implementation simplicity, no linear model for the grid synchronization systems with the dc rejection/estimation capability has yet been presented. The main aim of this article is to fill this research gap. It will be shown that developing such models facilitates the examination and the performance enhancement of the grid synchronization systems under study.
| Original language | English |
|---|---|
| Article number | 9173718 |
| Journal | IEEE Transactions on Power Electronics |
| Volume | 36 |
| Issue number | 4 |
| Pages (from-to) | 4237-4253 |
| Number of pages | 17 |
| ISSN | 0885-8993 |
| DOIs | |
| Publication status | Published - Apr 2021 |
Bibliographical note
Funding Information:Manuscript received March 18, 2020; revised June 26, 2020; accepted August 15, 2020. Date of publication August 21, 2020; date of current version November 20, 2020. This work was supported in part by the Deanship of Scientific Research, King Abdulaziz University, Jeddah, under Grant RG-12-135-39, and in part by VILLUM FONDEN under the VILLUM Investigator Grant 25920: Center for Research on Microgrids. Recommended for publication by Associate Editor H. L. Ginn, III. (Corresponding author: Saeed Golestan.) Saeed Golestan, Josep M. Guerrero, and Juan C. Vasquez are with the Department of Energy Technology, Aalborg University, DK-9220 Aalborg, Denmark (e-mail: sgd@et.aau.dk; joz@et.aau.dk; juq@et.aau.dk).
Funding Information:
The authors acknowledge with thanks the technical and financial supports of DSR and The Villum Foundation.
Publisher Copyright:
© 1986-2012 IEEE.
Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.
Keywords
- DC component
- frequency-locked loop (FLL)
- linear time-invariant (LTI)
- linear time-periodic (LTP)
- phase-locked loop (PLL)
- reduced-order generalized integrator (ROGI)
- second-order generalized integrator (SOGI)
- single-phase systems
- synchronization
- three-phase systems