Effect of short-circuit stress on the degradation of the SiO₂ dielectric in SiC power MOSFETs

This paper presents the impact of a short-circuit event on the gate reliability in planar SiC MOSFETs, which becomes more critical with increased junction temperature and higher bias voltages. The electrical waveforms indicate that a gate degradation mechanism takes place, showing a large gate leakage current that increases as the gate degrades more and more. A failure analysis has been performed on the degraded SiC MOSFET and then compared to the structure of a new device to identify possible defects/abnormalities. A Focused-Ion Beam cut is performed showing a number of differences in comparison to the new device: (i) cracks between the poly-silicon gate and aluminium source, (ii) metal particles near the source contact, and (iii) alterations in the top surface of the aluminium source. The defects have been correlated with the increase in gate-leakage current and drain-leakage current.